LCD Array Substrate Curved Metal Pattern for Three-Mask Fabrication

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Solution Overview

Problem

The existing liquid crystal display (LCD) device manufacturing processes are complex and costly, with four-mask processes still requiring multiple steps of cleaning, photoresist coating, exposure, and etching, leaving room for simplification.

Innovation Solution

The array substrate for LCD devices is fabricated using a three-mask process, where a metal pattern with at least one curved portion contacts the pixel electrode, increasing the side length between the gate line and the pixel electrode, preventing exposure of the gate line even if the passivation layer and gate insulating layer are over-etched, thus simplifying the process and reducing defects.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If four-mask processes are used to fabricate array substrate, then manufacturing precision can be maintained, but device complexity and loss of time increase due to multiple cleaning, photoresist coating, exposure, and etching steps

Engineering Contradiction:
Improvepattern formation precisionVSAvoidprocess complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent combines multiple process steps into fewer steps. Specifically, it merges the formation of the metal pattern and the pixel electrode into a single etching step using one photoresist pattern, eliminating the need for separate photoresist coating, exposure, and etching steps for each layer. This reduces the number of masks from four to three while maintaining pattern formation precision.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent applies preliminary action by forming the photoresist pattern to expose both the metal pattern region and the pixel electrode region simultaneously before etching. This preliminary patterning step allows subsequent etching to create multiple features in one operation, reducing overall process complexity and time.

Inventive Principle:
Principle #10Preliminary action

2Manufacturing precision

If four-mask processes are used to fabricate array substrate, then manufacturing precision can be maintained, but loss of time increases due to multiple repeated process steps

Engineering Contradiction:
Improvepattern formation precisionVSAvoidfabrication time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

The patent combines multiple process steps into fewer steps. Specifically, it merges the formation of the metal pattern and the pixel electrode into a single etching step using one photoresist pattern, eliminating the need for separate photoresist coating, exposure, and etching steps for each layer. This reduces the number of masks from four to three while maintaining pattern formation precision.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent enables continuous useful action by designing the etching process to simultaneously create the metal pattern and pixel electrode structures in one continuous etching operation, rather than requiring separate sequential operations. This continuity reduces idle time between steps and accelerates fabrication.

Inventive Principle:
Principle #20Continuity of useful action

3Ease of manufacture

If metal pattern side is straight and contacts pixel electrode, then manufacturing is simple, but reliability decreases when passivation layer and gate insulating layer are over-etched causing gate line exposure

Engineering Contradiction:
Improvepattern formation simplicityVSAvoiddefect prevention
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent applies curvature by designing the metal pattern side to have a curved portion instead of a straight edge. This curved geometry provides a buffer zone that prevents direct contact between the pixel electrode and gate line even when the passivation layer and gate insulating layer are over-etched, thereby preventing gate line exposure defects while maintaining ease of manufacture.

Inventive Principle:
Principle #14Spheroidality (Curvature)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces the number of manufacturing steps, increases productivity, and minimizes defects by ensuring the pixel electrode connects correctly to the metal pattern without contacting the gate line, enhancing the reliability and efficiency of the LCD device production.

Implementation Method 1

The liquid crystal 18 is dielectric anisotropic material having a property of spontaneous polarization

Methodology Applied
Scientific EffectDielectric anisotropy: Dielectric Permittivity

Implementation Method 2

The liquid crystal 18 is dielectric anisotropic material having a property of spontaneous polarization

Methodology Applied
Scientific EffectSpontaneous polarization: Polarisation

Implementation Method 3

When a voltage is applied, the liquid crystal 18 forms a dipole by the spontaneous polarization, and thus molecules of the liquid crystal are arranged by an electric field

Methodology Applied
Scientific EffectElectric field alignment: Electric Field

Implementation Method 4

Optical modulation occurs from the optical properties of the liquid crystal, which vary according to the arrangement of the liquid crystal

Methodology Applied
Scientific EffectOptical modulation: Electro-Optic Effects

Data Source

PatentUS7439088B2Liquid crystal display device and fabricating method thereof
Publication Date: 2008.10.21 LG DISPLAY CO LTD
  • US7439088B2 patent drawing
  • US7439088B2 patent drawing
  • US7439088B2 patent drawing

AI summary

An array substrate for a liquid crystal display device includes a substrate, a gate line and a data line crossing each other to define a pixel region, a thin film transistor at a crossing of the gate and data lines, a metal pattern over the gate line, a passivation layer exposing the substrate in the pixel region, a part of the thin film transistor and a part of the metal pattern, and a pixel electrode in the pixel region. The pixel electrode is connected to the part of the thin film transistor and contacts the part of the metal pattern. The metal pattern has at least one curved portion in a side contacting the pixel electrode.