TFT-LCD Fabrication Reducing Photo-Etching Steps
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing methods for fabricating TFT-LCD panels are complex and costly, requiring multiple photo-etching processes that increase the risk of contamination and decrease yield due to the complexity of the processes.
Innovation Solution
A method that simplifies the fabrication process by reducing the number of photo-etching processes from five to two, involving the formation of a transparent conductive layer and a first metal layer, followed by the creation of gate and pixel electrodes, and then the formation of source and drain electrodes, with a protecting layer, using IGZO semiconductor layer and SiOx or SiON insulating layers to minimize contamination and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If five photo-etching processes are used to fabricate TFT-LCD panel, then the manufacturing precision and reliability are improved, but the device complexity and manufacturing cost increase significantly
Solution Approach 1:
The patent combines multiple photo-etching processes into a single integrated process. Specifically, the gate electrode and pixel electrode are formed simultaneously in one photo-etching step, and the source/drain electrodes are formed in another unified step. This merging of previously separate processes reduces complexity while maintaining manufacturing precision through careful process integration and material layer design.
Solution Approach 2:
The patent employs universal process steps that serve multiple functions. The single photo-etching process for forming both gate and pixel electrodes simultaneously performs multiple patterning functions. Additionally, the metal layers and insulating layers are designed to serve multiple purposes in the final device structure, reducing the number of specialized process steps needed.
2Manufacturing precision
If five photo-etching processes are used to fabricate TFT-LCD panel, then the manufacturing precision is improved, but the productivity decreases due to increased contamination risk
Solution Approach 1:
By merging multiple photo-etching operations into fewer integrated steps, the patent reduces the cumulative exposure to contamination risks. Each additional photo-etching process introduces opportunities for dust and contaminant introduction; consolidating these steps minimizes the total number of process interfaces and handling operations, thereby improving yield rate while maintaining quality through careful process design.
Solution Approach 2:
The patent accelerates the fabrication process by eliminating intermediate steps and moving directly from keylay formation to final electrode patterning in fewer process cycles. This rushing through of the fabrication sequence reduces the time the product spends in vulnerable states where contamination could occur, thereby improving productivity and yield rate.
3Manufacturing precision
If five photo-etching processes are used to fabricate TFT-LCD panel, then the manufacturing precision is improved, but the loss of time increases due to multiple process steps
Solution Approach 1:
The patent merges multiple sequential photo-etching processes into fewer concurrent or integrated operations. By combining the formation of gate/pixel electrodes and source/drain electrodes into streamlined process sequences, the total fabrication time is reduced while maintaining manufacturing precision through careful process integration and material layer design.
Solution Approach 2:
The patent performs preliminary formation of metal layers and insulating layers in advance, with precise thickness control and material selection, so that subsequent photo-etching steps can proceed more quickly and efficiently. The preliminary preparation of layers with appropriate properties enables faster processing while maintaining final product quality.
Data Source
AI summary
A method for manufacturing a LCD panel includes providing a substrate defining a TFT region and a pixel region; forming a transparent conductive layer and a first metal layer on the substrate in that order; forming a gate line in the TFT region, and a pixel electrode within the pixel region via a first photo-etching process; forming an insulating layer and a semiconductor layer on the substrate in that order; removing the insulating layer and the semiconductor layer from the pixel region; removing the first metal layer from the pixel region; forming a second metal layer on the substrate; forming a source electrode and a drain electrode in the TFT region via a second photo-etching process, and forming a protecting layer above the substrate.