LCD Fabrication Method Reducing Mask Count via Layer Segmentation
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Solution Overview
Problem
The existing fabrication methods for liquid crystal display (LCD) devices require a large number of masking processes, making them expensive and environmentally harmful, with a need to reduce the total number of masks to improve production yield and cost efficiency.
Innovation Solution
A method for fabricating an LCD device using three masks, involving the sequential formation of a first conductive layer, insulation layer, semiconductor layer, and ohmic contact layer, with patterning to form gate lines, data lines, and electrodes, and the use of an organic insulation film to insulate gate lines, allowing for simultaneous formation of source, drain, and pixel electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a large number of masking processes are used in the fabrication method, then the TFT structure can be formed with good precision, but the production cost increases and environmental harm increases
Solution Approach 1:
The patent combines multiple masking processes into a single masking step by using a multi-layer conductive structure where the first, second, and third electrodes are formed simultaneously. This merging approach reduces the number of masks from multiple separate processes to one integrated process, lowering both cost and environmental impact while maintaining structural precision through the designed layer configuration.
Solution Approach 2:
The single mask used in the invention serves multiple functions: it defines the patterns for the first electrode, second electrode, and third electrode simultaneously, as well as establishing the gate line and data line structures. This multi-functional mask replaces what would traditionally require several specialized masks, achieving both cost reduction and precision maintenance.
2Manufacturing precision
If a large number of masking processes are used in the fabrication method, then the TFT structure can be formed with good precision, but the environmental harm increases
Solution Approach 1:
By merging multiple masking operations into one integrated masking process, the patent significantly reduces the number of chemical etching steps and mask disposal requirements. This consolidation maintains the necessary TFT structural precision while minimizing environmental harm by reducing waste generation and chemical usage associated with repeated masking cycles.
3Ease of manufacture
If the number of masks is reduced to three, then the production cost decreases and production yield improves, but the fabrication process complexity increases
Solution Approach 1:
The patent segments the electrode structure into three distinct conductive layers (first conductive layer for gate line, second conductive layer for data line and first electrode, third conductive layer for second electrode and third electrode). This segmentation allows a single mask to define multiple electrode patterns simultaneously, reducing mask count while managing process complexity through clear layer differentiation.
Solution Approach 2:
The invention resolves process complexity by adding a vertical dimension to the patterning process. Instead of using multiple masks in sequential planar steps, the patent uses stacked conductive layers where each layer is deposited and patterned in a specific sequence, allowing complex electrode arrangements to be achieved through vertical layering rather than multiple lateral masking steps.
Data Source
AI summary
A method for fabricating an LCD device includes forming sequentially a first conductive layer, a first insulation layer, a semiconductor layer, and an ohmic contact layer on a first substrate; forming a gate line by patterning the first conductive layer, the first insulation layer, the semiconductor layer, and the ohmic contact layer; exposing a first gate pad electrode connected with the gate line; insulating the gate line; forming a data line that intersects the gate line, wherein an electrode part is formed extending from the data line such that the electrode part is formed over the semiconductor layer and the ohmic layer, and defines an active pattern; forming a transparent electrode layer on the substrate including the electrode part; and forming source, drain, and pixel electrodes simultaneously by patterning at least one of the transparent electrode layer, the electrode part, and the ohmic contact layer.


