LCD Pixel Structure Using Isotropic Etching and Stacked Capacitor
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Solution Overview
Problem
The existing methods for fabricating liquid crystal display (LCD) pixel structures are costly due to the need for multiple photomasks and have insufficient capacitor capacity, as the capacitors composed of polysilicon, silicon oxide, and molybdenum are inadequate in many circumstances.
Innovation Solution
A method that reduces the number of masks required by using an isotropic etching process with a patterned photoresist layer to form the source/drain region and forms a stacked structure of silicon oxide and aluminum on the capacitor electrode to increase storage capacitance, thereby reducing fabrication costs and enhancing capacitor capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If standard fabrication process with multiple photomasks is used, then manufacturing precision is maintained, but fabrication cost increases
Solution Approach 1:
The patent combines multiple photomask steps into a single photomask process by using the same patterned photoresist layer for both source/drain region formation and capacitor electrode definition. This merging of functions reduces the number of photomasks from multiple to one, directly addressing the contradiction between fabrication cost and device complexity.
Solution Approach 2:
The patterned photoresist layer serves multiple functions: it acts as a mask for source/drain region formation, defines capacitor electrode patterns, and guides subsequent etching and deposition processes. This multi-functionality eliminates the need for separate photomasks for each step, reducing overall fabrication cost while maintaining manufacturing precision.
2Reliability
If capacitor is formed with standard materials (polysilicon, silicon oxide, molybdenum), then fabrication process is simple, but capacitor capacity is insufficient
Solution Approach 1:
The patent employs a composite capacitor structure combining multiple dielectric layers (silicon oxide, aluminum oxide) and conductive materials (molybdenum, aluminum). This composite approach increases capacitor capacity by utilizing materials with higher dielectric constants and optimized electrical properties, while the aluminum layer added during the same photomask process minimizes the increase in device complexity.
Solution Approach 2:
The patent transitions from a planar capacitor structure to a stacked multi-layer structure by adding vertical dimensions with multiple dielectric and conductive layers. This dimensional change significantly increases capacitor capacity without requiring additional photomask steps, as the stacked structure is formed during the same fabrication sequence.
3Ease of manufacture
If isotropic etching is used to form source/drain region, then number of masks is reduced, but etching precision control becomes more difficult
Solution Approach 1:
The patent controls isotropic etching precision by adjusting etching parameters such as etchant concentration, temperature, and etching time. By optimizing these parameters, the process achieves the desired source/drain region dimensions and capacitor electrode patterns while maintaining manufacturing precision despite the isotropic nature of the etching.
Solution Approach 2:
The patent replaces traditional anisotropic etching (which relies on crystallographic orientation for precision) with isotropic etching controlled by chemical parameters and photoresist mask design. This substitution reduces the number of masks needed while maintaining precision through parameter optimization rather than mechanical or crystallographic constraints.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach decreases the overall fabrication cost by reducing the number of masks needed and increases the capacitor capacity by forming a stacked structure that enhances storage capacitance, improving the efficiency of the pixel structure.
Implementation Method 1
performing an isotropic etching process by using the patterned photoresist layer as mask
Implementation Method 2
performing an isotropic etching process by using the patterned photoresist layer as mask to remove a portion of the electrode layer in both vertical and horizontal direction
Implementation Method 3
performing a first ion implantation process by using the patterned photoresist layer as mask to form a source/drain region
Data Source
AI summary
A pixel structure includes a patterned semiconductor layer disposed on a transistor region of the substrate, a first capacitor electrode disposed on a capacitor region of the substrate, a gate dielectric layer disposed on the first capacitor electrode, a gate disposed on a channel region of the patterned semiconductor layer, a second capacitor electrode, a dielectric layer, and an aluminum capacitor electrode sequentially disposed on the gate dielectric layer of the capacitor region, a first dielectric layer disposed on the gate and the aluminum capacitor electrode, at least one first wire disposed in the first dielectric layer for electrically connecting source/drain region of the patterned semiconductor layer and the aluminum capacitor electrode, a second dielectric layer disposed on the first wire, and a first transparent conductive layer disposed on the second dielectric layer and connected to the first wire.