Multi-Layer Storage Capacitor Fabrication for LCD Panels
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Solution Overview
Problem
Conventional semiconductor fabrication methods for display devices require multiple photomasks, increasing costs and resulting in insufficient storage capacitance due to undoped poly-silicon layers in storage capacitors, which affects display quality.
Innovation Solution
A semiconductor structure with a multi-layer storage capacitor is fabricated using a method that reduces the number of photomasks required, involving a semiconductor layer, inter-layer dielectric layers, and electrodes to form a pixel structure with improved capacitance, where the semiconductor layer is doped and interconnected to enhance storage capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional fabricating methods with multiple photomasks are used, then the storage capacitance can be maintained at basic levels, but the fabrication cost increases significantly
Solution Approach 1:
The patent combines the formation of the storage capacitor with the TFT fabrication process by using the same doped poly-silicon layer for both the TFT channel and the storage capacitor electrode. This merging of functions eliminates the need for separate photomask steps for the storage capacitor, reducing fabrication cost while maintaining adequate storage capacitance through the multi-layer structure.
Solution Approach 2:
The patent transitions from a single-layer storage capacitor to a multi-layer storage capacitor structure by adding vertical stacking of dielectric layers and electrodes. This dimensional change increases the storage capacitance without requiring additional planar photomask steps, as the enhanced capacitance is achieved through the third dimension (vertical stacking) rather than lateral expansion.
2Reliability
If doped poly-silicon layers are used in storage capacitor area, then the storage capacitance is significantly increased, but the fabrication process complexity increases
Solution Approach 1:
The doped poly-silicon layer serves multiple functions: it acts as the channel layer for the TFT and simultaneously serves as one of the electrodes for the storage capacitor. This multi-functionality allows the storage capacitor to achieve high capacitance through doping without requiring separate fabrication processes, as the same doping step accomplishes both TFT channel formation and storage capacitor electrode preparation.
Solution Approach 2:
The poly-silicon layer is doped during the TFT fabrication process before the storage capacitor structure is fully assembled. This preliminary doping action prepares the storage capacitor electrode with high carrier concentration and conductivity in advance, enabling the subsequent formation of high-capacitance multi-layer structure without requiring additional doping steps.
3Ease of manufacture
If fewer photomasks are used, then the fabrication cost is reduced, but the manufacturing precision and control over capacitor formation may be compromised
Solution Approach 1:
The gate structure of the TFT serves as a self-aligned mask during the doping process, automatically defining the precise boundaries of the doped regions without requiring separate photomasks. This self-service mechanism ensures high manufacturing precision for the storage capacitor electrode formation, as the doping is automatically confined to the correct areas by the existing gate structure, eliminating alignment errors that would occur with additional photomasks.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method reduces fabrication costs by minimizing photomask usage and significantly increases storage capacitance, leading to improved display quality in liquid crystal display panels.
Implementation Method 1
A doping process is performed to form a source and a drain in the semiconductor layer in the active element area
Implementation Method 2
a first inter-layer dielectric layer is formed to cover a semiconductor layer
Data Source
AI summary
A method for fabricating a semiconductor structure with a multi-layer storage capacitor is provided. A substrate having an active element area and a storage capacitor area is provided. By sequentially fabricating a semiconductor layer, a first inter-layer dielectric (ILD) layer, a gate and a first electrode, a source and a drain in the semiconductor layer in the active element area, a second ILD layer, a patterned conductive layer served as a pixel electrode, a patterned third ILD layer, a plurality of contact windows in the first, second and third ILD layers for exposing the source, the drain, parts of the patterned conductive layer and the first electrode, a second electrode and a source/drain conductive line, the semiconductor structure with the multi-layer storage is obtained in consequence.