Solid-State Devices TRIZ Cases

Conserved polysilicon sections absorb stray light to reduce optical crosstalk, simplifying fabrication and improving image resolution.

A CMOS image sensor uses an intermediary P-type layer to isolate photo diodes on an N-type epitaxial substrate.

Curved pixel apertures diffract light in varying directions, reducing diffraction stripes that blur images captured by cameras behind transparent displays.

Vertical fin structures in the transfer gate expand channel width, reducing image lag caused by incomplete charge removal from photodiodes.

Laser heating weakens the bond between faulty LED chips and circuit substrates, enabling selective removal without damaging surrounding components.

Curved overcoat micro lenses alter optical paths to reduce total internal reflection and improve light extraction efficiency in electroluminescent displays.

Stepped encapsulation layers prevent oxygen and moisture permeation through side portions, enhancing device durability without increasing structural complexity.

Plasma treatment smooths Bosch etched via-holes, allowing a dual-layer barrier metal to improve coverability and reduce film stress.

Localized trench isolation structures compensate for pattern density variations during chemical mechanical polishing to equalize polysilicon gate layer thickness.

Dummy pixels emit varied light colors at display edges to minimize boundary interference, resolving color shift issues in high screen-to-body ratio devices.

A lateral pn junction beneath a buried oxide layer uses a field plate electrode to modify the electric field distribution.

Doped polysilicon layers form a multi-layer storage capacitor that increases capacitance while reducing photomask fabrication costs.

Laser-drilled discharging holes vent gases from organic layers, preventing pixel shrinkage and maintaining display reliability.

Counter substrate power supply lines join array substrate lines through conductive members, eliminating luminance gradients caused by high line resistance.

A mesh structured driving voltage line shields a capacitor from data line interference, reducing crosstalk while maintaining high definition displays.

Direct metal gate stress transfer to SOI FinFET channels eliminates separate mask layers, boosting switching speed while reducing current leakage.

A metal electrode inverts bonding and reflective layers via heat treatment to improve semiconductor interface characteristics.

Triangular epitaxial protrusions act as bottom electrodes and nucleation sites, controlling conducting filament positions to improve memory window stability.

A light emitting module uses a patterned conductive layer to connect devices and transfer heat directly to a dissipation unit.

A platinum complex with a nitrogen-containing bidentate chelate enhances rigidity and planarity for efficient near-infrared emission.

Embedding light sensitive units within the OLED module functional layer reduces optical propagation paths and increases received signal intensity.

A germanium-containing metal growth layer promotes homogeneous nucleation of silver cathodes on organic substrates.

A phase change material layer modulates light color in an organic light emitting diode lighting device.

A MEMS physical unclonable function uses a control element to alter ambient parameters for generating multiple cryptographic responses.

Segmented gate stacks in a vertical memory device reduce RC delay differences between word lines, improving programming speeds.

Segmented multifunctional layer with trap and blocking regions surrounds vertical channel layers in 3D semiconductor memory devices.

Adjusting the organic layer thickness to X+120N nm simplifies full color display manufacturing by removing complex multi-dopant systems.

Composite host system with optimized triplet energies resolves charge transport and efficiency roll-off trade-offs in blue OLEDs.

A bridge wiring with a convex shape electrically connects pixel electrodes while altering light reflection angles to minimize color banding.

A light emitting diode structure uses a peripheral protective layer and a convex reflective electrode to enhance electrical isolation.

Collective grinding of bonded substrates forms curved liquid crystal panel edges, reducing stress-induced cracking and shortening production time.

A photodiode array incorporates a lower conductive part beneath the electrode to increase pixel capacitance and dynamic range.

Organic-filled via holes segment inorganic layers to diffuse stress, preventing damage when the flexible display bends at small radii.

Lateral positioning of the resistive memory element beside the MuGFET fin minimizes step height differences and reduces integration overhead.

An asymmetric channel doping profile in a depletion-type MOSFET suppresses gate-aided breakdown while maintaining threshold voltage stability.

A memory cell uses a dielectric structure with varying thickness to store data states within an integrated transistor footprint.

Composite organic materials replace silicon photodiodes to maintain sensitivity while increasing pixel resolution density.

A resistor material layer mediates current conduction in filamentary memory cells to enable complete conducting filament removal.

A graded metal oxide portion forms in resistive random access memory cells through chemical vapor deposition of a metal material on a metal oxide layer.

Modified inorganic mixed powder integrated into OLED panels emits far-infrared light and negative ions to mitigate electromagnetic radiation pollution.

A spacer patterning method uses sacrificial and spacer patterns as etch barriers to define hard mask layers for semiconductor fabrication.

OLED display panel design segments insulation layers to minimize light interference with thin film transistors while facilitating ink-jet printing processes.

Segmented amorphous silicon nitride layers resolve the contradiction between high sealing density and bending tolerance by absorbing moisture through cracks.

Self-aligned shallow trench isolation through a silicon rich charge storage layer reduces programming time and series resistance in NAND flash.

Automated multi-layer fill generation optimizes pattern density across circuit layers, reducing manufacturing defects and capacitive effects.

Angled dopant implants create lateral charge balance in gated and non-gated trenches, reducing specific on-state resistance.

Segmenting plate voltage supply lines reduces load capacitance and access time in semiconductor memory devices.

Depositing a single semiconductor layer directly on the substrate removes contiguous grain boundaries that degrade electrical characteristics and reliability.

A semiconductor memory device positions select transistor layers above and below the memory cell array to streamline wiring connections.

Angled ion implantation creates asymmetric source and drain heights, reducing carryover capacitance at the drain side and lowering leakage current.