Polysilicon Gate Thickness Uniformity via Localized Trench Isolation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The polysilicon chemical mechanical polishing process often results in uneven thickness of the polysilicon gate layers due to differences in pattern density and pressure, leading to issues like dishing effects and affecting device performance and manufacturing reliability.
Innovation Solution
A method is introduced to evaluate and ensure uniformity of the polysilicon gate layer thickness by forming trench isolation structures with varying densities, using a mask layer and pad oxide layer, and performing chemical mechanical polishing to equalize the thickness across different areas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Shape
If polysilicon chemical mechanical polishing process is used to planarize the polysilicon layer, then the surface flatness is improved, but the thickness uniformity deteriorates due to dishing effect in low pattern density areas
Solution Approach 1:
The patent applies local quality by creating different trench isolation structures in different areas of the substrate. Specifically, first trench isolation structures are formed in the dense trenches area with different dimensions compared to second trench isolation structures in the sparse trenches area. This local differentiation compensates for the polishing rate variations caused by pattern density differences, thereby maintaining thickness uniformity across the entire wafer surface while achieving surface flatness.
2Ease of manufacture
If the polysilicon layer is polished uniformly across the entire wafer, then the processing simplicity is improved, but the thickness control in different pattern density areas deteriorates
Solution Approach 1:
The patent implements local quality by designing different trench isolation structures for different pattern density areas. The first trench isolation structures in dense areas and second trench isolation structures in sparse areas have different dimensions, creating localized compensation that maintains thickness control without requiring complex area-specific polishing processes.
Solution Approach 2:
The patent applies preliminary action by pre-forming trench isolation structures with different dimensions in different areas before the polysilicon layer deposition and polishing steps. This preliminary structuring compensates for anticipated polishing rate variations, allowing subsequent uniform polishing across the entire wafer while maintaining thickness control in different pattern density areas.
3Manufacturing precision
If trench isolation structures with different dimensions are formed in dense and sparse trenches areas, then the thickness uniformity is improved, but the device complexity increases
Solution Approach 1:
The patent achieves thickness uniformity through local quality by forming trench isolation structures with different dimensions only in specific areas (dense vs. sparse trenches areas) rather than uniformly across the entire wafer. This localized approach provides the necessary thickness control while minimizing overall structural complexity compared to a completely uniform structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method achieves even polysilicon gate layer thickness, preventing dishing effects and enhancing manufacturing reliability by ensuring consistent thickness across the wafer surface, thus improving device performance and lithography and etching processes.
Implementation Method 1
a planarization process is performed for removing portions of the polysilicon gate layer
Data Source
AI summary
A method of evaluating the uniformity of the thickness of the polysilicon gate layer is provided. A substrate having a dense trenches area and a sparse trenches area is provided. A plurality of first trench isolation structures are formed in the sparse trenches area of the substrate and a plurality of second trench isolation structures are simultaneously formed in the dense trenches area of the substrate. A mask layer is formed between the gaps of the first and the second trench isolation structures. A portion of the first trench isolation structures of the sparse trenches area is then removed. Then, the mask layer is removed until the surface of the substrate is exposed. A polysilicon gate layer is formed over the substrate. Finally, a planarization process is performed to remove a portion of the polysilicon gate layer.