Multi-Layer Fill Polygon Generation for Circuit Density Optimization
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Solution Overview
Problem
Conventional planarization methods in integrated circuit manufacturing result in uneven surfaces due to differing material densities, leading to manufacturing defects like holes and bridging faults, and require tedious manual processes to optimize pattern density across multiple layers.
Innovation Solution
A software-based approach that analyzes circuit layers to identify empty regions, generates a pattern of fill polygons to optimize pattern density, and allows simultaneous optimization of multiple layers by adding geometric fill elements, ensuring compliance with specified density constraints and minimizing capacitive effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional planarization methods are used, then manufacturing process is simple, but surface uniformity deteriorates leading to holes and bridging faults
Solution Approach 1:
The patent applies preliminary action by performing density optimization and adding fill structures to circuit layers before the planarization process. This advance preparation ensures that materials are distributed more uniformly across the layer, preventing surface unevenness and manufacturing defects during subsequent planarization, rather than attempting to correct issues after they occur.
Solution Approach 2:
The patent changes the density parameter of materials in circuit layers by automatically analyzing empty regions and adding fill structures to achieve target density values. This parameter adjustment ensures more uniform material distribution across the layer, improving surface uniformity and preventing defects like holes and bridging faults during manufacturing.
2Productivity
If manual processes are used to optimize pattern density, then control over density constraints is precise, but productivity deteriorates due to tedious manual intervention
Solution Approach 1:
The patent implements self-service through an automated system that performs density optimization without requiring manual intervention. The software automatically analyzes circuit layers, identifies empty regions, calculates appropriate fill structures, and places them to meet density constraints. This self-automating approach maintains precise control over density compliance while dramatically improving productivity by eliminating tedious manual processes.
Solution Approach 2:
The patent replaces manual mechanical processes with an automated software-based system. Instead of manually analyzing layouts and placing fill structures, the system uses computational algorithms to automatically perform density analysis and optimization, substituting human labor with automated computing while maintaining or improving precision in meeting density constraints.
3Loss of time
If fill structures are added to multiple layers separately, then each layer can be optimized individually, but time consumption increases due to sequential processing
Solution Approach 1:
The patent merges the density optimization process for multiple layers into a single simultaneous operation. The system analyzes and adds fill structures to multiple circuit layers together in one processing pass, rather than treating each layer separately. This combining of operations significantly reduces total processing time while maintaining the ability to meet layer-specific density constraints through coordinated fill placement across all layers.
Solution Approach 2:
The patent creates a universal density optimization system that can simultaneously handle multiple layers with different density requirements. The software is designed to perform a single multi-functional operation that optimizes density across various layers in one process, making the system adaptable to different layer configurations and density constraints without requiring separate processing for each layer.
Data Source
AI summary
Techniques are disclosed for optimizing the pattern density in the circuit layout design of a circuit layer. A layer in circuit design is analyzed to define empty regions that can be filled with fill polygons (referred to hereafter as “fill” regions). Next, a pattern of fill polygons is generated. After the fill polygons have been defined, the layout design for the layer is divided into separate areas or “windows,” and a target density for each window is determined. Once this target density for the window has been determined, the fill polygons required to most closely approach this target density are generated and added to the circuit layout design. This process may be repeated with progressively different (e.g., smaller) fill polygons, until each window meets or exceeds both the specified minimum density and complies with the specified maximum density gradient. Additionally, some implementations may allow a user to simultaneously optimize the density of multiple layers of a circuit by adding fill polygons to multiple layers of a circuit design simultaneously. Representations of sections of a multilayer fill structure will then be added to corresponding layers the circuit design until a specified target density is met.