Semiconductor Memory Device Plate Line Segmentation
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Solution Overview
Problem
Conventional semiconductor memory devices with ferroelectric substances face challenges in achieving high-speed operation, low power consumption, and reduced size due to excessive load capacitances and high resistance in plate lines, leading to increased access time and power consumption, and layout area issues.
Innovation Solution
The semiconductor memory device addresses these challenges by arranging plate voltage supply lines in the same direction as word lines, allowing for stabilized plate line voltage and reduced dimensionality of plate line voltage supply circuits, with the option to form these lines from the same or different layers than bit lines, and selectively connecting them to achieve high-speed operation and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If plate lines are used to drive memory cells, then data storage capability is achieved, but load capacitances become excessively large and access time increases
Solution Approach 1:
The patent divides the memory cell array into multiple blocks along the column direction, with each block having its own dedicated plate line. This segmentation reduces the total capacitance that each plate line must drive, thereby reducing access time while maintaining data storage capability through the ferroelectric capacitors in each segmented block.
2Reliability
If plate lines are used to drive memory cells, then data storage capability is achieved, but resistance of plate lines becomes high and power consumption increases
Solution Approach 1:
By segmenting the memory array into multiple blocks with dedicated plate lines, the patent reduces the total resistance of the plate line system. Each segmented plate line drives fewer capacitors, resulting in lower overall resistance and reduced power consumption for driving the plate lines while maintaining reliable data storage.
3Loss of time
If plate line division system is used, then load capacitances are reduced and access time is improved, but layout area increases
Solution Approach 1:
The patent introduces a block division concept that organizes memory cells into multiple blocks along the column direction. This dimensional organization allows plate lines to be segmented and assigned to specific blocks, reducing load capacitance and access time while maintaining compact layout through systematic arrangement of the blocked structure.
4Speed
If MOS transistors of high driving ability are used to drive plate lines, then plate line driving speed is improved, but power consumption and layout area increase
Solution Approach 1:
Instead of using high-driving-capability MOS transistors to drive a single large plate line, the patent segments the memory array into multiple blocks, each with its own plate line. This allows smaller, lower-power transistors to drive each segmented plate line effectively, achieving the required driving speed while reducing overall power consumption and layout area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables high-speed operation, reduced power consumption, and compact design by stabilizing plate line voltage, minimizing the area occupied by plate line voltage supply circuits, and enhancing integration and shape stability, thereby improving data holding and reducing variations in memory cell characteristics.
Implementation Method 1
Transition of the polarized state of a ferroelectric substance shows hysteresis characteristics, and remnant polarization exists in the ferroelectric substance even when a voltage applied to the ferroelectric substance becomes 0
Data Source
AI summary
A semiconductor memory device includes plural memory cells MC arranged in a matrix, plural bit lines BL and plural plate line voltage supply lines SCP which are arranged in a row direction, plural sense amplifier circuits SA which are arranged in a column direction and are electrically connected to the respective bit lines, plural plate line voltage supply circuits CPD which are arranged in the column direction and drive the plate line voltage supply lines SCP, and means for electrically connecting the plate line voltage supply lines SCP with the plural plate lines CP, wherein the respective plate voltage supply lines SCP are electrically connected, at different positions on the same plate line CP, to the plate line CP.