Memory Device With Dielectric Thickness Modulation For Nonvolatile Storage
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Solution Overview
Problem
Current memory devices, such as DRAMs, do not retain data when power is cut off, while nonvolatile memory devices like MRAMs, RRAMs, and PCRAMs have limitations in storing data using different principles, necessitating a new approach for a memory device that can store different states with applied voltages without increasing device area.
Innovation Solution
A memory cell with a different-dielectric-thickness structure is formed, comprising a substrate with a transistor region and a memory region, where a dielectric structure with a thin and thick portion is used to store data, allowing for distinct states when different voltages are applied, and the memory cell is integrated without adding area burden.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If a nonvolatile memory device is used to retain data without power, then data retention capability is improved, but device complexity and manufacturing limitations increase due to specialized structures for magnetization storage, phase change materials, or resistance switching
Solution Approach 1:
The patent combines DRAM transistor structure with a dielectric memory cell structure into a single integrated device. The memory cell includes a bottom electrode, a dielectric layer, and a top electrode, integrated with the transistor to form a unified structure that achieves nonvolatile storage without requiring separate specialized memory device components.
Solution Approach 2:
The dielectric layer serves multiple functions: it acts as the memory storage medium through thickness modulation, functions as an insulating layer between electrodes, and enables both volatile and nonvolatile operation modes. This multi-functionality reduces the need for additional specialized components.
2Quantity of substance
If different dielectric thicknesses are used to store data states, then storage capability is improved, but manufacturing precision requirements increase due to the need for controlled thin and thick dielectric portions
Solution Approach 1:
A uniform dielectric layer is deposited first as a preliminary step, then selectively removed in the memory region to create the thin portion while leaving the thick portion elsewhere. This preliminary uniform deposition simplifies the manufacturing process by establishing a controlled baseline before creating the thickness variation needed for data storage.
Solution Approach 2:
The dielectric layer is segmented into distinct thin and thick portions within the same memory device structure. The thin dielectric portion stores data in one state while the thick dielectric portion provides a reference or alternative state, enabling binary or multi-level storage through spatial segmentation of the dielectric thickness.
3Duration of action of stationary object
If device area is increased to accommodate nonvolatile memory structures, then data retention is improved, but integration density decreases
Solution Approach 1:
The memory cell structure is nested within the transistor structure, with the bottom electrode, dielectric layer, and top electrode integrated into the existing device footprint. The dielectric memory cell is positioned to utilize space efficiently alongside or within the transistor components, achieving nonvolatile storage without proportionally increasing the overall device area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution provides a stable memory window and long retention time, suitable for embedded DRAM applications, with the ability to control the memory window by tuning the area ratio of the top electrode, simplifying fabrication and reducing costs.
Implementation Method 1
The popular dynamic random access memory (DRAM) cell includes a switch and a capacitor
Implementation Method 2
RRAMs store data by changes in electric resistance
Data Source
AI summary
A memory device includes a transistor, a memory cell, and an interconnect layer. The transistor includes a bottom source/drain portion, a channel portion, and a top source/drain portion stacked from bottom to top and a gate structure surrounding the channel portion. The memory cell includes a nanowire bottom electrode, a first dielectric layer, a second dielectric layer, and a top electrode. The first dielectric layer laterally surrounds the nanowire bottom electrode. The second dielectric layer is over the nanowire bottom electrode and the first dielectric layer. The second dielectric layer is in contact with a top surface of the nanowire bottom electrode and a sidewall of the first dielectric layer. The top electrode covers the second dielectric layer. The interconnect layer is over the transistor and the memory cell to interconnect the transistor and the memory cell.