Spacer Patterning Technology Hard Mask Etch Process
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Solution Overview
Problem
The Spacer Patterning Technology (SPT) process in semiconductor device fabrication is complex and costly due to the need for additional masks and etch/deposition processes, which complicates pattern formation and reduces productivity, especially when forming patterns under 40 nm using conventional photoresist technologies.
Innovation Solution
A method that simplifies the SPT process by forming a hard mask layer, a sacrificial layer pattern, and a spacer pattern, using these as etch barriers to selectively etch the hard mask layer, and then removing the spacer pattern to form patterns in both cell and peripheral regions with improved etch characteristics, reducing the need for additional masks and processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the SPT process uses additional masks and etch/deposition processes to form isolation layer patterns, then pattern formation capability is improved, but manufacturing cost increases and productivity decreases
Solution Approach 1:
The patent merges the isolation layer pattern formation with the main device pattern formation by using a single mask that defines both the device patterns and the isolation regions. This integration eliminates the need for separate mask processes for isolation layers, thereby maintaining pattern formation capability while significantly improving productivity by reducing the total number of fabrication steps.
Solution Approach 2:
The mask used in the SPT process is designed to serve multiple functions: it defines the device patterns, defines the isolation layer patterns, and enables both etch and deposition processes to be performed in an integrated manner. This multi-functionality of the mask process eliminates the need for additional dedicated masks for isolation layers, reducing manufacturing complexity and improving productivity.
2Manufacturing precision
If the SPT process uses additional masks and etch/deposition processes to form isolation layer patterns, then pattern formation capability is improved, but manufacturing cost increases
Solution Approach 1:
The patent merges the isolation layer pattern formation with the main device pattern formation by using a single mask that defines both the device patterns and the isolation regions. This integration eliminates the need for separate mask processes for isolation layers, thereby maintaining pattern formation capability while significantly reducing manufacturing cost by eliminating material and process steps.
Solution Approach 2:
The mask used in the SPT process is designed to serve multiple functions: it defines the device patterns, defines the isolation layer patterns, and enables both etch and deposition processes to be performed in an integrated manner. This multi-functionality of the mask process eliminates the need for additional dedicated masks for isolation layers, reducing manufacturing complexity and cost.
3Device complexity
If conventional photoresist technologies are used for patterning, then process simplicity is maintained, but resolution capability deteriorates for patterns under 40 nm
Solution Approach 1:
The patent introduces a spacer layer as an intermediary element that enables sub-lithographic pattern formation. The spacer is deposited conformally on the mask and then anisotropically etched to transfer the pattern at a reduced pitch. This intermediary spacer approach allows conventional photoresist to achieve resolutions below its native capability, effectively bridging the gap between simple photoresist processes and advanced patterning requirements.
Solution Approach 2:
The patent changes the physical and chemical parameters of the patterning process by introducing spacer materials with different etch selectivity and deposition characteristics. By controlling the spacer thickness, etch conditions, and material composition, the process achieves sub-40 nm resolution while maintaining compatibility with conventional photoresist workflows, thus improving manufacturing precision without completely overhauling the process simplicity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances mass productivity and process margins by simplifying the SPT process, improving critical dimension uniformity, and reducing costs by eliminating the need for additional masks and processes, while ensuring accurate pattern formation and reducing misalignment concerns.
Implementation Method 1
selectively etching the hard mask layer of the first region by using the spacer pattern as an etch barrier while protecting the hard mask layer of the second region from being etched
Implementation Method 2
forming a hard mask layer over an etch target layer that extends across a first region and a second region; forming a sacrificial layer pattern over the hard mask layer of the first region
Implementation Method 3
etching the hard mask layer of the first and second regions by using the cut mask pattern as an etch barrier
Data Source
AI summary
A method includes forming a hard mask layer over an etch target layer that extends across first and second regions, forming a sacrificial layer pattern over the hard mask layer of the first region, removing the sacrificial layer pattern after forming a spacer pattern on side walls thereof, selectively etching the hard mask layer of the first region by using the spacer pattern as an etch barrier while protecting the hard mask layer of the second region from being etched, removing the spacer pattern, forming a cut mask pattern over the hard mask layer of the first and second regions, etching the hard mask layer of the first and second regions by using the cut mask pattern as an etch barrier, removing the cut mask pattern, and forming patterns in the first and second regions respectively by using the hard mask layer of the first and second regions as an etch barrier and etching the etch target layer.