Stacked Select Transistor Layers for Semiconductor Memory Chip Area Reduction
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Solution Overview
Problem
The high density memory cell array in resistive memory devices requires numerous select transistors, increasing the chip area due to the need for both bit line and word line select transistors, which complicates the layout and increases the overall semiconductor memory device size.
Innovation Solution
The semiconductor memory device configuration includes a memory cell array with select transistors positioned below and above the memory cell array in a stacked manner, allowing for a more efficient connection of wiring lines to the peripheral circuit without crossing, thereby reducing the need for select transistors in the peripheral circuit layer and minimizing chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If select transistors are disposed in the peripheral circuit layer to select bit lines and word lines, then the memory cell array can be selected, but the chip area increases due to the large region required for select transistors
Solution Approach 1:
The patent moves select transistors from the peripheral circuit layer to stacked positions above and below the memory cell array in the vertical dimension. This dimensional transition allows select transistors to access bit lines and word lines from multiple sides, reducing the need for select transistors in the peripheral circuit layer and thereby reducing chip area.
2Ease of operation
If numerous select transistors are disposed in the peripheral circuit layer, then bit lines and word lines can be selected, but the layout becomes complicated and the overall device size increases
Solution Approach 1:
By positioning select transistors in stacked configurations above and below the memory cell array, the patent simplifies the layout by eliminating the need for numerous select transistors in the peripheral circuit layer. This vertical arrangement reduces layout complexity while maintaining the selection functionality.
3Ease of operation
If select transistors are disposed above and below the memory cell array in a stacked manner, then connectivity to peripheral circuits is improved, but wiring line connections must be managed in three dimensions
Solution Approach 1:
The patent utilizes the vertical dimension to route wiring lines from stacked select transistors to the memory cell array. By extending wiring lines in the vertical direction, the patent achieves improved connectivity while managing the increased routing complexity through three-dimensional space.
Data Source
AI summary
A semiconductor memory device comprises: a memory cell array comprising first wiring lines, second wiring lines extending crossing the first wiring lines, and memory cells at intersections of the first and second wiring lines, the memory cells being stacked perpendicularly to a substrate, each memory cell comprising a variable resistance element; a first select transistor layer comprising a first select transistor operative to select one of the first wiring lines; a second select transistor layer comprising a second select transistor operative to select one of the second wiring lines; and a peripheral circuit layer on the substrate, the peripheral circuit layer comprising a peripheral circuit that controls a voltage applied to one of the memory cells. The first select transistor layer is provided below the memory cell array perpendicularly to the substrate. The second select transistor layer is provided above the memory cell array perpendicularly to the substrate.