Multifunctional Layer Segmentation for 3D Memory Cell Isolation
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Solution Overview
Problem
In 3-dimensional semiconductor memory devices, charge transport between memory cells due to a shared charge storage layer affects data retention and reliability, making it difficult to ensure reliable operation.
Innovation Solution
The semiconductor memory device incorporates interlayer insulating and conductive patterns stacked alternately, with vertical channel layers and a multifunctional layer that includes trap regions, blocking regions, and sacrificial regions to prevent charge transport between cells, enhancing data retention and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a charge storage layer is formed to surround the entire surfaces of sidewalls of the channel layer in 3-dimensional semiconductor memory devices, then the manufacturing process is simplified, but charges stored in a specific memory cell are transported to another memory cell along the charge storage layer, causing data retention issues
Solution Approach 1:
The charge storage layer is segmented into isolated regions corresponding to individual memory cells using blocking insulating layers. These blocking layers are formed at intersections between word lines and channel layers, dividing the continuous charge storage layer into discrete segments that prevent charge transport between adjacent memory cells while maintaining the 3-dimensional structure.
Solution Approach 2:
Blocking insulating layers are introduced as intermediary structures between adjacent charge storage regions. These intermediary layers act as barriers that prevent direct charge transport between memory cells while allowing the charge storage layer to maintain its continuous formation along channel layer sidewalls, thus resolving the contradiction between manufacturing simplicity and charge isolation.
2Productivity
If memory cells are arranged 3-dimensionally to increase integration density, then the capacity per area is improved, but charge transport between cells along the charge storage layer reduces reliability
Solution Approach 1:
The charge storage layer is segmented into isolated regions corresponding to individual memory cells using blocking insulating layers. These blocking layers are formed at intersections between word lines and channel layers, dividing the continuous charge storage layer into discrete segments that prevent charge transport between adjacent memory cells while maintaining the 3-dimensional structure.
Solution Approach 2:
The blocking insulating layers are selectively formed only at specific locations where word lines intersect with channel layers, creating localized isolation regions. This local modification allows charge storage layers to remain continuous in most areas for manufacturing simplicity while providing targeted isolation precisely where charge transport between cells occurs.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively prevents charge transport between memory cells, thereby improving the reliability and data retention characteristics of the semiconductor memory device.
Implementation Method 1
a tunnel insulating layer formed to surround sidewalls of each of the vertical channel layers
Implementation Method 2
the multifunctional layer includes trap regions disposed at intersections between the vertical channel layers and the conductive patterns, respectively, and disposed to be in contact with the tunnel insulating layer
Implementation Method 3
blocking regions disposed to be in contact with the trap regions and the conductive patterns
Data Source
AI summary
A semiconductor memory device and a method of manufacturing the same are provided. The device includes interlayer insulating patterns and conductive patterns stacked alternately, vertical channel layers formed through the interlayer insulating patterns and the conductive patterns, a tunnel insulating layer formed to surround sidewalls of each of the vertical channel layers, and a multifunctional layer formed to surround the tunnel insulating layer. The multifunctional layer includes trap regions disposed at intersections between the vertical channel layers and the conductive patterns, respectively, and disposed to be in contact with the tunnel insulating layer, blocking regions disposed to be in contact with the trap regions and the conductive patterns, and sacrificial regions disposed between adjacent ones of the blocking regions.