Resistive Memory Lateral MuGFET Integration
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Solution Overview
Problem
Current programmable resistive RAM technologies face challenges in integrating resistive memory cells with CMOS logic technology due to topological height differences caused by vertical fabrication, which affects write speed and current requirements, and increases integration overhead.
Innovation Solution
The integration of a resistive memory element with a multi-gate field effect transistor (MuGFET) select device, where the memory element is positioned laterally to the fin of the MuGFET, allowing for a smaller programmable volume and minimizing step height differences, enabling efficient current delivery and reduced leakage currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If vertical fabrication of programmable resistive memory is used, then memory cell structure is formed, but topological height differences are generated between memory areas and CMOS circuit areas
Solution Approach 1:
The patent transitions from vertical stacking to lateral arrangement by positioning the resistive memory element horizontally adjacent to the MuGFET fin structure. This dimensional change eliminates vertical height differences between memory and logic areas, enabling planar integration with CMOS technology while maintaining functional performance.
Solution Approach 2:
Instead of placing the memory element above the transistor (vertical approach), the patent inverts the arrangement by positioning it laterally beside the fin structure. This inversion resolves the topological height issue by distributing components in the horizontal plane rather than stacking them vertically.
2Use of energy by moving object
If larger programmable volume is used, then current delivery is improved, but write speed decreases and current requirements increase
Solution Approach 1:
The patent optimizes the programmable volume dimensions to achieve optimal current density. By carefully controlling the volume size and shape, the design maintains sufficient current delivery capability while minimizing the volume to enable faster write speeds and reduce current requirements, balancing energy efficiency and performance.
Solution Approach 2:
The patent creates high current density locally at the contact interface between the MuGFET and resistive memory element. The lateral positioning and optimized contact geometry concentrate current flow efficiently into the programmable volume, achieving effective current delivery without requiring large overall volume, thus maintaining fast write speeds.
3Adaptability or versatility
If vertical stacking of memory element is used, then integration with CMOS is attempted, but integration overhead increases due to topological height differences
Solution Approach 1:
The lateral MuGFET structure serves dual purposes: it provides the select transistor function and simultaneously creates a planar interface that simplifies integration with CMOS logic. The fin structure acts as both the transistor channel and a low-profile connection element, reducing the need for additional height-compensation structures and simplifying the overall integration process.
Data Source
AI summary
A memory device includes a multi gate field effect transistor (MuGFET) having a fin with a contact area. A programmable memory element abuts the fin contact area.