Array Substrate Layering for Lower Pixel-Data Line Parasitic Capacitance
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Solution Overview
Problem
Current liquid crystal display panels face high power consumption due to large parasitic capacitance between the pixel electrode and the data line, which interferes with data signal transmission and increases energy usage.
Innovation Solution
The array substrate design includes a first transistor with a data line disposed close to the substrate and a pixel electrode positioned away from the substrate, ensuring a significant vertical distance to minimize parasitic capacitance, and uses a second transistor with the data line and gate in the same layer made of the same material to reduce manufacturing complexity and capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the pixel electrode and data line are disposed close to each other to reduce overall device size, then the display panel achieves compact dimensions, but large parasitic capacitance is generated between the pixel electrode and data line causing high power consumption
Solution Approach 1:
The patent applies dimensional separation by stacking the pixel electrode and data line in different vertical layers (pixel electrode in upper layer, data line in lower layer), transforming a two-dimensional planar arrangement into a three-dimensional configuration. This reduces parasitic capacitance while maintaining compact display area through vertical integration
Solution Approach 2:
The data line is nested within the transparent connecting electrode structure, with the data line positioned in the lower layer and the pixel electrode in the upper layer. This nested arrangement allows close proximity for signal transmission while minimizing parasitic capacitance through layered separation
2Ease of manufacture
If the data line is disposed on the side of the first active layer close to the substrate, then the structure is simplified and manufacturing is easier, but parasitic capacitance between data line and pixel electrode increases
Solution Approach 1:
The data line is positioned in the lower layer while the pixel electrode is in the upper layer, creating vertical separation. This dimensional change allows the data line to be close to the substrate for manufacturing simplicity while avoiding close proximity to the pixel electrode, thus reducing parasitic capacitance
Solution Approach 2:
The transparent connecting electrode acts as an intermediary structure between the data line and pixel electrode. It provides electrical connection while physically separating the data line and pixel electrode in different layers, reducing parasitic capacitance
3Loss of energy
If oxide TFTs and LTPS TFTs are used to minimize parasitic capacitance, then power consumption is reduced, but manufacturing process complexity increases
Solution Approach 1:
Different transistor types are applied locally: oxide TFTs are used in the display region where low parasitic capacitance is critical for pixel electrode operation, while LTPS TFTs are used in the non-display region for gate driver circuits. This localized material selection optimizes performance while managing manufacturing complexity
Solution Approach 2:
The patent establishes a unified manufacturing process framework that can accommodate both oxide TFTs and LTPS TFTs through shared fabrication steps. The common process architecture reduces the actual complexity increase despite using multiple transistor types
Data Source
AI summary
Provided is an array substrate. The array substrate includes a display region and a non-display region located at a periphery of the display region, wherein the array substrate includes a substrate; a first transistor and a second transistor that are disposed on the substrate, wherein the first transistor is disposed in the display region, and the second transistor is disposed in the non-display region; and a data line and a pixel electrode that are disposed in the display region, wherein the data line is disposed on a side of the first active layer close to the substrate and is lapped with the first active layer, and the pixel electrode is disposed on a side of the first gate facing away from the substrate and is lapped with the first active layer.