LCD Array Substrate Three-Mask Process Aperture Ratio
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Solution Overview
Problem
The existing methods for fabricating liquid crystal display (LCD) devices with four mask processes result in increased fabrication time and product cost due to leakage currents and wavy noise caused by exposed semiconductor layers and protruding intrinsic amorphous silicon, which degrade the thin film transistor characteristics and reduce the aperture ratio.
Innovation Solution
A method using three mask processes to fabricate the array substrate, where the active layer is covered by the gate electrode, preventing exposure to light and reducing leakage currents, and eliminating the protrusion of semiconductor layers outside metal lines, thereby reducing wavy noise and improving the aperture ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If four mask processes are used to fabricate the array substrate, then the manufacturing precision can be maintained, but the fabrication time and product cost increase
Solution Approach 1:
The patent combines multiple mask processes into a reduced number of mask processes. Specifically, it merges the formation of the gate electrode and gate line into a single mask process, and combines the formation of source/drain electrodes and data lines into another integrated process, thereby reducing the total number of mask steps while maintaining manufacturing precision
Solution Approach 2:
The patent designs mask patterns that serve multiple functions simultaneously. For example, the gate electrode pattern is formed to also define the gate line structure, and the source/drain electrode formation process simultaneously creates the data line patterns, making each mask process multi-functional and reducing overall process complexity
2Ease of manufacture
If the active layer is exposed to light, then the fabrication process is simplified, but leakage currents increase and thin film transistor characteristics degrade
Solution Approach 1:
The patent applies a passivation layer to the active layer before subsequent processing steps. This preliminary protective action prevents light exposure and contamination during fabrication, thereby maintaining thin film transistor characteristics while still allowing for simplified fabrication processes
Solution Approach 2:
The passivation layer acts as an intermediary between the active layer and the external environment (light). It protects the active layer from harmful light exposure during fabrication without complicating the overall manufacturing process, thus maintaining both ease of manufacture and device reliability
3Ease of manufacture
If semiconductor layers protrude outside metal lines, then the mask alignment tolerance is relaxed, but wavy noise increases and aperture ratio decreases
Solution Approach 1:
The patent applies different structural characteristics to different regions. The semiconductor layer is confined within metal line regions where electrical connection is needed, while extending beyond metal lines in non-critical areas only when necessary for electrical connection, thereby optimizing both alignment tolerance and aperture ratio locally
Solution Approach 2:
The patent resolves the conflict by considering the vertical dimension and electrical connection requirements. The semiconductor layer protrusion is permitted only where it can establish proper electrical connection, transforming the problem from a purely planar alignment issue to a three-dimensional electrical connectivity solution
Data Source
AI summary
A liquid crystal display device includes a gate line and a gate electrode connected to the gate line, on a substrate; a gate insulating layer on the gate electrode and the gate line; an active layer on the gate insulating layer over the gate electrode; an ohmic contact layer on the active layer; first source and drain electrodes on the ohmic contact layer; second source and drain electrodes connected to the first source and drain electrodes, respectively; a data line extending from the source electrode and crossing the gate line to define a pixel region; and a pixel electrode in the pixel region and extending from the second drain electrode.