LDD Length Control in Array Substrate Manufacturing
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Solution Overview
Problem
The existing methods for manufacturing metal oxide semiconductor array substrates face challenges in controlling the length of lightly doped drains (LDD) due to the restrictive conditional requirements for gate line width and LDD length, resulting in low control flexibility and poor feasibility.
Innovation Solution
A method involving the formation of a gate pattern with a gate photoresist pattern on a substrate, where the temperature of the gate photoresist pattern is altered to change its width, allowing for the precise control of LDD length without simultaneously meeting the conditional requirements for gate line width, using a manufacturing device with temperature processing units for heating or cooling treatments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the gate line width is controlled by prolonging or shortening the etching time, then the LDD length can be controlled, but the control flexibility is reduced and the conditional requirements for gate line width and LDD length cannot be met simultaneously
Solution Approach 1:
The patent divides the gate pattern formation into two independent stages: first forming the gate pattern with a first photoresist, then forming the LDD pattern with a second photoresist. This segmentation allows each pattern to be controlled independently, resolving the contradiction between precise LDD length control and control flexibility.
Solution Approach 2:
The patent introduces a second photoresist as an intermediary to form the LDD pattern separately from the gate pattern. This intermediary enables independent control of LDD length without affecting gate line width, achieving both conditional requirements simultaneously.
2Manufacturing precision
If the gate line width is determined first, then the LDD length is also determined, so that the length of the LDD cannot be changed any more
Solution Approach 1:
The patent segments the patterning process into independent gate pattern formation and LDD pattern formation steps. The gate pattern is formed first with a first photoresist, then the LDD pattern is formed with a second photoresist. This allows the LDD length to be adjusted independently after the gate line width is determined.
Solution Approach 2:
The patent makes the LDD length adjustable and dynamic by using a separate photoresist process. The second photoresist can be applied with different dimensions to achieve various LDD lengths while maintaining the fixed gate line width, providing operational flexibility.
3Reliability
If the two processes of exposing the LDD and etching the gate cannot be performed simultaneously, then the conditional requirements for gate line width and LDD length are mutually restricted
Solution Approach 1:
The patent segments the exposure and etching processes into separate stages with different photoresists. The gate pattern is formed in the first stage, then the LDD pattern is formed in the second stage. This segmentation allows both processes to be performed sequentially without mutual restriction, meeting both conditional requirements.
Solution Approach 2:
The patent introduces a second photoresist as an intermediary material to enable the LDD patterning process to occur after gate pattern formation. This intermediary allows the conditional requirements for both gate line width and LDD length to be met without conflict.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the control flexibility and feasibility of LDD length control, allowing for LDDs to be formed that meet specific length requirements without affecting the gate line width, thereby improving the manufacturing process efficiency.
Implementation Method 1
altering a temperature of the gate photoresist pattern, so as to enable the width of the gate photoresist sub-pattern in the gate photoresist pattern to be changed
Implementation Method 2
performing cooling treatment to the gate photoresist pattern, so as to enable the width of the gate photoresist sub-pattern in the gate photoresist pattern to be shortened
Data Source
AI summary
Embodiments of the present invention disclose a manufacturing method for an array substrate and corresponding manufacturing device, which belong to the technical field of metal oxide semiconductor. The method comprises: forming an active layer, a gate insulating layer and a gate metal layer successively on a substrate; forming a gate pattern with a gate photoresist pattern on the substrate having the gate metal layer; altering a temperature of the gate photoresist pattern, so as to enable the width of the gate photoresist sub-pattern in the gate photoresist pattern to be changed; forming lightly doped drains (LDDs) at two sides of a preset area of the active layer sub-pattern in the active layer of the substrate having the changed gate photoresist pattern, the preset area being a projection area of the gate sub-pattern on the active layer sub-pattern, the length of each of the LDDs being (a−b)/2, wherein a is the width of the gate photoresist sub-pattern in the changed gate photoresist pattern, b is the width of the gate sub-pattern; stripping the changed gate photoresist pattern. The embodiment of the present invention mitigates or alleviates the problem of relatively low control flexibility and relatively poor feasibility to the LDD length, which improves the control flexibility and feasibility to the LDD length, and can be used for manufacturing an array substrate.