High-Voltage LDMOS Buffer Layer Design for Breakthrough Voltage
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Solution Overview
Problem
The use of an N-type epitaxial layer as a buffer layer in high-voltage LDMOS integrated devices complicates the manufacturing process and increases costs, as it requires thickness increases to improve operating voltage, leading to premature depletion and breakdown under reverse bias.
Innovation Solution
A high-voltage LDMOS integrated device structure using deep N-wells and low-voltage N-wells as longitudinal voltage-withstanding buffer layers, with P-wells as body areas, allowing for improved voltage withstand without the need for an epitaxial layer, simplifying the process and reducing costs by leveraging common CMOS process structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an N-type epitaxial layer is used as a longitudinal voltage-withstanding buffer layer and its thickness is increased to improve operating voltage, then the breakthrough voltage of the drain is improved, but the manufacturing process becomes complicated and costs increase
Solution Approach 1:
The patent changes the doping concentration parameter of the buffer layer by using a P-type substrate with a specific resistance range (50-200 ohms·cm) instead of changing the thickness of an N-type epitaxial layer. This parameter substitution resolves the contradiction by achieving voltage withstand through material property adjustment rather than geometric dimension increase, thereby avoiding process complexity and cost increases.
2Reliability
If an N-type epitaxial layer is used as a longitudinal voltage-withstanding buffer layer and its thickness is increased to improve operating voltage, then the breakthrough voltage of the drain is improved, but the manufacturing cost increases
Solution Approach 1:
The patent substitutes the thickness parameter with doping concentration parameter by using a P-type substrate with controlled resistance (50-200 ohms·cm). This eliminates the need for expensive thick epitaxial layer fabrication while achieving the same voltage withstand capability, thereby reducing manufacturing costs.
Data Source
AI summary
The invention discloses a high-voltage LDMOS integrated device, which is interdigitally structured in a plan view and which including: a first area corresponding to a source fingertip area, wherein a first sectional structure of the first area particularly includes: a first drain; and a first longitudinal voltage-withstanding buffer layer located below the first drain and consisted of a first deep N-well and a first low-voltage N-well, wherein the first low-voltage N-well is located in the first deep-N well, and the first deep-N well is located in a P-type substrate; and a second area non-overlapping with the first area, wherein a second sectional structure of the second area particularly includes: a second drain; and a second longitudinal voltage-withstanding buffer layer located below the second drain and consisted of a second deep N-well and a second low-voltage N-well.