LDMOS Buried Layer Fabrication via Low-Energy Ion Implantation
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Solution Overview
Problem
Conventional semiconductor power devices require high-energy ion implantation processes to form buried layers, which are costly and not feasible in many fabrication facilities, limiting the production of high-breakdown voltage and low on-resistance LDMOS transistors.
Innovation Solution
A semiconductor power device with multiple epitaxial layers and buried layers formed using a low-energy ion implantation process, where the epitaxial layers and buried layers are strategically positioned to reduce on-resistance and maintain high breakdown voltage, eliminating the need for high-energy implantation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If high-energy ion implantation process is used to form P type buried layer, then sufficient implantation depth is achieved to form first conduction path, but manufacturing cost increases and feasibility decreases
Solution Approach 1:
The patent divides the single deep implantation process into multiple sequential implantation steps with different energies. The P type buried layer is formed through multiple implantations at energies of 1 MeV, 2 MeV, and 3 MeV, where each step contributes to the overall depth and doping profile. This segmentation allows achieving the required implantation depth without requiring a single high-energy implantation step that would be costly and technically challenging.
Solution Approach 2:
The patent performs preliminary low-energy implantations to form initial P type regions before subsequent higher-energy implantations. The first implantation at 1 MeV creates a shallow P type layer, which serves as a foundation for deeper implantations. This preliminary action enables the final deep P type buried layer to be formed more effectively and with better control over the doping profile.
2Reliability
If additional P type buried layers are formed to reduce resistance, then on-resistance decreases, but ion-implantation energy requirements increase
Solution Approach 1:
The patent implements multiple P type buried layers at different depths, each formed by sequential implantation steps. The first P type buried layer is formed at a shallower depth with lower energy, while the second P type buried layer is formed deeper with higher energy. This segmented approach reduces the total resistance by providing multiple conduction paths without requiring any single implantation to achieve excessive depths that would demand prohibitively high energies.
Solution Approach 2:
The patent varies the implantation energy and doping concentration parameters across different implantation steps to optimize the resistance reduction. By adjusting the energy levels (1 MeV, 2 MeV, 3 MeV) and doping doses for each P type buried layer, the patent achieves cumulative resistance reduction while keeping individual implantation energies within feasible ranges for standard fabrication equipment.
3Adaptability or versatility
If LDMOS device structure is used, then integration with control and logic circuits is improved, but breakdown voltage and on-resistance optimization becomes more difficult
Solution Approach 1:
The patent applies local quality by creating spatially varying doping profiles in the LDMOS device. The P type buried layers are selectively positioned at specific depths and locations to locally enhance the breakdown voltage characteristics. The drift region is doped with P type impurities at varying concentrations at different depths, creating localized regions that optimize both the electric field distribution and the breakdown voltage while maintaining compatibility with standard LDMOS integration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables the fabrication of semiconductor power devices with reduced on-resistance and high breakdown voltage without the need for high-energy ion implantation, improving manufacturing feasibility and cost-effectiveness.
Implementation Method 1
a first conductivity type buried layer formed in the well
Implementation Method 2
an epitaxial layer formed on the semiconductor substrate
Data Source
AI summary
A semiconductor power device and a method of fabricating the same are provided. The semiconductor power device involving: a first conductivity type semiconductor substrate; an epitaxial layer formed on the semiconductor substrate; a second conductivity type well formed in the semiconductor substrate and the epitaxial layer; a drain region formed in the well; an oxide layer that insulates a gate region from the drain region; a first conductivity type buried layer formed in the well; a second conductivity type drift region surrounding the buried layer; and a second conductivity type TOP region formed between the buried layer and the oxide layer.