High-Voltage LDMOS Layout With Stable Channel Length and Fewer Masks
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Solution Overview
Problem
The integration of high voltage P-type and N-type lateral double-diffused MOS (LDMOS) devices in a single chip is challenging due to the complexity of fabrication steps, particularly the high temperature drive-in annealing process, which makes it difficult to maintain a stable channel length and uniformly distribute dopants, leading to limitations in adjusting the channel length and increasing the number of masks required in the manufacturing process.
Innovation Solution
The approach involves forming body regions and LDD regions using the same mask pattern before the gate process, applying a drive-in process to ensure stable channel length by implanting dopants at a smaller tilt angle, and reducing the number of masks by forming these regions before gate electrode formation, thereby simplifying the manufacturing process and improving dopant distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the integration of high voltage devices (PLDMOS and NLDMOS) is attempted in a single chip, then device functionality is improved, but fabrication complexity increases
Solution Approach 1:
The patent combines PLDMOS and NLDMOS devices into a single chip structure, integrating both device types within one semiconductor substrate. This merging approach enables dual functionality while sharing common fabrication processes, thereby reducing overall fabrication complexity despite the versatility gain
Solution Approach 2:
The patent employs universal fabrication steps that can form both PLDMOS and NLDMOS devices through the same process sequence. The fabrication method uses common dopant implantation, oxidation, and etching steps that serve multiple device formation purposes, reducing the number of specialized process steps required
2Ease of manufacture
If the channel length is not maintained consistently, then manufacturing simplicity is improved, but device performance deteriorates
Solution Approach 1:
The patent performs dopant implantation to form body and LDD regions before gate electrode formation. This preliminary action establishes the channel boundaries and length definition early in the process, ensuring consistent channel length across devices while simplifying subsequent manufacturing steps
Solution Approach 2:
The patent utilizes the inherent diffusion characteristics of dopants during thermal processing to automatically define and stabilize channel length. The dopant diffusion profiles self-organize to create well-defined body and LDD regions that establish consistent channel dimensions without requiring additional precision control steps
3Ease of manufacture
If the number of masks is reduced, then manufacturing cost is improved, but manufacturing precision may worsen
Solution Approach 1:
The patent employs masks that serve multiple functions in the fabrication process. Single masks are used to define both body regions and LDD regions, and later masks serve dual purposes for gate formation and alignment features. This multi-functionality reduces the total number of masks required while maintaining adequate pattern definition accuracy
Solution Approach 2:
The patent adjusts dopant implantation parameters (energy, angle, concentration) to achieve precise region definition without requiring additional masking steps. By optimizing these parameters, the process maintains manufacturing precision while reducing mask count and associated costs
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method allows for the successful integration of high voltage P-type and N-type LDMOS devices in a single chip, reducing the number of masks required, stabilizing channel length, and lowering ON resistance, while maintaining high breakdown voltage and fast switching response.
Implementation Method 1
The semiconductor device and manufacturing method utilize the inherent diffusion characteristics of dopants to form body and LDD regions
Implementation Method 2
The semiconductor device and manufacturing method utilize the inherent diffusion characteristics of dopants to form body and LDD regions
Data Source
AI summary
A semiconductor device includes a deep well region located on a substrate, a drift region located in the deep well region, a first gate electrode that overlaps with the first body region and the drift region, a second gate electrode that overlaps with the second body region and the drift region, a first source region and a second source region located in the first and second body regions, respectively, a drain region located in the drift region and disposed between the first gate electrode and the second gate electrode, a silicide layer located on the substrate, a first non-silicide layer located between the drain region and the first gate electrode, wherein the first non-silicide layer extends over a top surface of the first gate electrode, and a first field plate contact plug in contact with the first non-silicide layer.