LDMOS Doped Region Depth Optimization for On-Resistance Reduction
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Solution Overview
Problem
Conventional LDMOS devices face issues with high on-resistance and parasitic loss due to parasitic capacitance, necessitating an improved device structure.
Innovation Solution
A field LDMOS device is fabricated with a gate structure, source and drain regions of a first conductivity type, an isolation region surrounding the source and drain, and a doped region of a second conductivity type with a deeper bottom than the isolation region, along with a base region at the semiconductor substrate surface, to reduce contact resistance and enhance current flow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a conventional LDMOS device structure is used, then the device can be manufactured with standard processes, but the on-resistance is relatively high
Solution Approach 1:
The patent applies local quality by creating a doped region with a specific conductivity type that surrounds the isolation region, with its bottom positioned deeper than the isolation region bottom. This localized doped region provides selective electrical properties in a specific area of the device, reducing on-resistance at the critical interface between the isolation region and the semiconductor substrate while maintaining standard manufacturing processes.
2Device complexity
If a conventional LDMOS device structure is used, then the device structure is simpler, but parasitic loss due to parasitic capacitance is inevitable
Solution Approach 1:
The patent introduces a doped region as an intermediary element between the isolation region and the semiconductor substrate. This doped region acts as a mediator that reduces parasitic capacitance by providing a controlled electrical pathway, thereby reducing parasitic loss without significantly complicating the overall device structure or manufacturing process.
3Ease of manufacture
If the doped region bottom is positioned at the same depth as the isolation region bottom, then the manufacturing process is simpler, but contact resistance is not optimized
Solution Approach 1:
The patent resolves this contradiction by extending the doped region in the vertical dimension, positioning its bottom deeper than the isolation region bottom. This dimensional change creates a three-dimensional doped region that provides improved electrical contact and reduced contact resistance, while the deeper extension can be achieved through standard sequential doping processes without significantly complicating manufacturing.
Data Source
AI summary
A LDMOS includes a gate structure disposed on the surface of a semiconductor substrate, a source region having a first conductivity type, a drain region having the first conductivity type, an isolation region surrounding the source/drain regions, a doped region having a second conductivity type, and a base region having the second conductivity type formed in the doped region. The source/drain regions are respectively disposed on two sides of the gate structure. The doped region surrounds the isolation region, and the bottom of the doped region is deeper than the bottom of the isolation region. The base region is disposed at the surface of the semiconductor substrate.