LDMOS Drain-Via Structure for Lower On-Resistance and High Breakdown
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Solution Overview
Problem
High voltage and high current applications impose challenges on laterally-diffused metal-oxide-semiconductor (LDMOS) devices, particularly in terms of device size, specific on-resistance, and reliability of high current short-circuit capability, due to design rules that increase device size and on-resistance.
Innovation Solution
The transistor structure incorporates a field isolation barrier layer with a drain via that penetrates through it, eliminating the need for metal silicide on the drain region and optimizing the spacing between the drain electrode and the silicide blocking layer, combined with features like shallow trench isolation and reduced surface electric fields to enhance breakdown voltage and reduce on-resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If design rules are applied to ensure reliability under high current conditions, then breakdown voltage is improved, but device size and specific on-resistance increase
Solution Approach 1:
The patent extracts and removes the metal silicide layer from the drain region, eliminating the need for silicide blocking layer and associated design rules. This extraction allows the drain electrode to be directly formed on the drain region, reducing device size while maintaining reliability through optimized spacing between the drain electrode and source region
Solution Approach 2:
The patent transitions from a planar layout constrained by silicide blocking rules to a vertical integration approach where the drain electrode is positioned in a different spatial dimension relative to the source region. This dimensional change allows optimized spacing without being constrained by traditional lateral design rules
2Reliability
If design rules are applied to ensure reliability under high current conditions, then breakdown voltage is improved, but specific on-resistance increases
Solution Approach 1:
By removing the metal silicide layer and silicide blocking layer from the drain region, the patent eliminates the additional resistance introduced by these layers and their required spacing, thereby reducing specific on-resistance while maintaining reliability through direct control of the drain electrode positioning
Solution Approach 2:
The patent changes the critical parameter from spacing relative to silicide blocking layer to spacing between drain electrode and source region. This parameter change allows optimization of the spacing to minimize on-resistance while ensuring reliable high current operation
3Reliability
If metal silicide and silicide blocking layer are used on drain region, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent extracts and removes the metal silicide layer and silicide blocking layer from the drain region, simplifying the device structure by eliminating unnecessary layers and reducing the number of manufacturing steps required while maintaining reliability through optimized electrode spacing
Solution Approach 2:
Instead of adding metal silicide to improve reliability, the patent inverts the approach by removing silicide entirely from the drain region and relying on optimized geometric spacing and material selection to achieve the same reliability goal with simpler structure
Data Source
AI summary
A transistor structure can include: a source region and a drain region located in a semiconductor region; a gate dielectric layer located on the upper surface of the semiconductor region; a field isolation barrier layer located on the semiconductor region, and extending laterally from the gate dielectric layer at least above the drain region and covering the upper surface of the drain region, where the field isolation barrier layer includes at least one drain via on the upper surface of the drain region; and a drain electrode filling the drain via to be in contact with the drain region.