LDMOS Drift Region Width for Tight-Pitch Memory Integration

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Solution Overview

Problem

Traditional Laterally Diffused MOSFET (LDMOS) devices face a trade-off between on-state resistance and drain breakdown voltage, limiting their utility in tight-pitch environments such as embedded memory applications, where high breakdown voltage is required while maintaining low on-state resistance.

Innovation Solution

A high-voltage MOSFET device architecture with a narrow drift region is designed, allowing the depletion zone to extend fully across the drift region, increasing breakdown voltage while reducing device size, and optimizing device spacing for tight-pitch environments.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If light doping is used on the drain side to provide a wide depletion layer with high blocking voltage, then drain breakdown voltage is improved, but lateral spacing between devices must be increased which limits utility in tight-pitch environments

Engineering Contradiction:
Improvedrain breakdown voltageVSAvoidlateral spacing between devices
Core Design Contradiction:
ReliabilityVSLength of moving object

Solution Approach 1:

The patent transitions from traditional lateral depletion layer extension to vertical depletion layer extension by reducing drift region width. This dimensional change allows the depletion zone to extend vertically across the full width of the drift region, achieving high breakdown voltage without increased lateral spacing between devices

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent changes the critical parameter of drift region width to be sufficiently small, enabling the depletion zone to fully deplete free carriers across the entire drift region width. This parameter change allows simultaneous achievement of high breakdown voltage and compact lateral footprint for tight-pitch integration

Inventive Principle:
Principle #35Parameter changes

2Length of moving object

If device size is reduced for tight-pitch environments, then lateral spacing is improved, but maintaining high breakdown voltage becomes difficult

Engineering Contradiction:
Improvedevice sizeVSAvoiddrain breakdown voltage
Core Design Contradiction:
Length of moving objectVSReliability

Solution Approach 1:

By reducing drift region width and enabling vertical depletion extension, the patent achieves high breakdown voltage in a compact lateral footprint. The depletion zone extends vertically across the full drift region width rather than laterally, allowing small device size without sacrificing breakdown voltage

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively raises the drain breakdown voltage and reduces the size of LDMOS devices, enabling them to be compatible with higher density memory applications by allowing closer device spacing and reducing costs associated with tighter pitch integration.

Implementation Method 1

The portion of the drift region overlaid by the gate is bordered by semiconducting material forming a depletion zone with a reverse-biased PN junction when the controllable channel is off

Methodology Applied
Scientific EffectDepletion zone formation: Electric Field

Implementation Method 2

forming a depletion zone with a reverse-biased PN junction when the controllable channel is off

Methodology Applied
Scientific EffectReverse bias: Electric Field

Implementation Method 3

a voltage applied to the gate electrode can control whether a conductive channel forms between the source and the drain regions

Methodology Applied
Scientific EffectField effect: Electric Field

Data Source

PatentUS10043899B1Laterally diffused MOSFET for embedded memory applications
Publication Date: 2018.08.07 SEMICON COMPONENTS IND LLC
  • US10043899B1 patent drawing
  • US10043899B1 patent drawing
  • US10043899B1 patent drawing

AI summary

A Laterally Diffused MOSFET (LDMOS) device architecture particularly suitable for use in tight pitch environments such as for line drivers in an integrated memory application. In one embodiment, an illustrative high-voltage MOSFET device includes: a body (a semiconductor of a first conductivity type), a source region (a semiconductor of a second conductivity type) at a source active area and positioned within or adjacent to the body, a drift region (a lightly-doped semiconductor of the second conductivity type) positioned adjacent to the body, and a gate overlying at least a portion of the body and at least a portion of the drift region to form a controllable channel between the source region and the drift region. To increase the drain breakdown voltage, a width dimension of the drift region is formed to be sufficiently small for a depletion zone to extend across a full width of the drift region.