LDMOS Epi Cavity Uniformity via Dummy Gate Mediator
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Solution Overview
Problem
The formation of epi semiconductor material in the drain regions of LDMOS devices is often incomplete or irregular due to exposure of the isolation structure, leading to reduced device performance or failure in forming conductive contacts.
Innovation Solution
A method involving the formation of an isolation structure in the substrate with a channel-side edge positioned vertically below the gate and a drain-side edge positioned below a dummy gate, creating an epi cavity in the drain region with the substrate separating the isolation structure from the epi cavity, allowing for uniform growth of epi semiconductor material.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the epi cavity is formed in the drain region exposing the isolation structure, then the epi cavity can be formed in the drain region, but the growth of epi semiconductor material becomes non-uniform leading to incomplete filling
Solution Approach 1:
A dummy gate structure is introduced as an intermediary element positioned over the drain-side edge of the isolation structure. This dummy gate acts as a mediator that prevents direct exposure of the isolation structure edge during epi cavity formation, thereby enabling uniform epi semiconductor material growth while still allowing the epi cavity to be formed in the drain region. The dummy gate structure is subsequently removed after serving its protective function.
Solution Approach 2:
The dummy gate structure is formed in advance before the epi cavity formation process. This preliminary action positions a protective structure over the drain-side edge of the isolation structure prior to etching the epi cavity, ensuring that the isolation structure edge is not exposed during subsequent processing steps. This advance preparation prevents the uniformity issue before it occurs.
2Device complexity
If the epi semiconductor material volume is reduced in the drain region, then the device structure is simplified, but device performance is reduced or complete device failure occurs
Solution Approach 1:
The dummy gate structure serves as a temporary intermediary that enables complete filling of the epi cavity without adding permanent complexity to the device structure. By using this temporary structure during fabrication, the process achieves reliable device performance with adequate epi semiconductor material volume while avoiding permanent structural complications.
Solution Approach 2:
The dummy gate structure functions as a disposable element used only during the fabrication process. It is formed temporarily to enable uniform epi material growth, then removed after serving its purpose. This approach allows achievement of reliable device performance without permanently increasing device complexity or requiring complex structural modifications.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Ensures complete and uniform filling of the epi cavity, enhancing the performance of LDMOS transistors by maintaining the volume of epi semiconductor material in the drain region and facilitating the formation of conductive contacts.
Implementation Method 1
epi semiconductor material that is grown in cavities formed in the substrate
Data Source
AI summary
One illustrative integrated circuit product disclosed herein includes a gate structure positioned above a semiconductor substrate, a source region and a drain region, both of which include an epi semiconductor material, wherein at least a portion of the epi semiconductor material in the source and drain regions is positioned in the substrate. In this example, the IC product also includes an isolation structure positioned in the substrate between the source region and the drain region, wherein the isolation structure includes a channel-side edge and a drain-side edge, wherein the channel-side edge is positioned vertically below the gate structure and wherein a portion of the substrate laterally separates the isolation structure from the epi semiconductor material in the drain region.