LDMOS ESD Protection via Narrow Bulk Pick-Up Regions

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Solution Overview

Problem

Conventional LDMOS devices have inferior electrostatic discharge (ESD) abilities compared to dedicated ESD devices, necessitating a redesign to enhance their ESD capabilities while maintaining high voltage applications.

Innovation Solution

The design includes a semiconductor device with a gate electrode, source/drain region, and bulk pick-up regions of opposite conductivity types, where the bulk pick-up regions are narrower than the source/drain regions and physically spaced apart by a common source region, optimizing the layout for improved ESD performance and reduced chip area.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional LDMOS device structure is used, then LDMOS functionality is achieved, but electrostatic discharge ability is inferior

Engineering Contradiction:

Improveelectrostatic discharge abilityVSAvoiddevice structure

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The device is divided into multiple legs (first LDMOS device and second LDMOS device) that are connected in parallel. Each leg has its own source region, drain region, and bulk pick-up region, allowing the ESD current to be distributed across multiple paths, thereby enhancing overall electrostatic discharge capability while maintaining individual LDMOS functionality

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The LDMOS device structure is designed to serve dual purposes: maintaining its primary LDMOS functionality for high voltage applications while simultaneously providing electrostatic discharge protection. The shared bulk pick-up region and interconnected source/drain regions enable the device to function as both an operational amplifier component and an ESD protection device

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Power

If gate width is increased to increase drive current, then LDMOS performance improves, but chip area increases

Engineering Contradiction:

Improvedrive currentVSAvoidchip area

Core Design Contradiction:

PowerVSArea of stationary object

Solution Approach 1:

Multiple LDMOS devices share common source regions, drain regions, and bulk pick-up regions. The source regions and drain regions are interconnected through shared contacts, merging multiple device functions into a compact structure that achieves high drive current without proportionally increasing chip area

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The device structure utilizes vertical stacking and three-dimensional arrangement of regions. The bulk pick-up regions extend in the vertical dimension and are positioned at different depths, allowing efficient use of chip area while maintaining high drive current capability through multiple parallel conduction paths

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS7781834B2Robust ESD LDMOS device

Publication Date: 2010.08.24 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A semiconductor device includes a gate electrode over a semiconductor substrate, wherein the gate electrode has a gate width direction; a source/drain region in the semiconductor substrate and adjacent the gate electrode, wherein the source/drain region has a first width in a direction parallel to the gate width direction; and a bulk pick-up region in the semiconductor substrate and abutting the source/drain region. The bulk pick-up region and the source/drain region have opposite conductivity types. The bulk pick-up region has a second width in the width direction, and wherein the second width is substantially less than the first width.