LDMOS Transistor Field Plate Design for High Breakdown Voltage
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Solution Overview
Problem
Laterally Diffused Metal Oxide Semiconductor (LDMOS) transistors face challenges in achieving high breakdown voltage and minimizing drain-to-source specific-on resistance, particularly due to non-ideal potential distribution and high electric fields at the drain and drift region interface, which limits their performance in high-side operating applications.
Innovation Solution
The power transistor design incorporates a buried oxide layer and a field plate to enhance the reduced surface field (RESURF) effect and reduce metal component of the drain-to-source on-resistance, with a dielectric layer thickness optimized to achieve peak breakdown voltage and a field plate extension that minimizes source-substrate coupling, allowing for improved electrical isolation and reduced specific-on resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the dielectric layer thickness is increased to reduce electric field at the drain-drift region interface, then the breakdown voltage is improved, but the device area and capacitance increase
Solution Approach 1:
The patent extends the field plate into the trench region, transitioning from a planar field plate configuration to a three-dimensional structure that utilizes the vertical dimension and trench space. This dimensional change allows the field plate to provide enhanced field control and breakdown voltage improvement without proportionally increasing the lateral device area, as the extension occurs partially in the vertical and lateral trench dimension rather than solely in the planar area.
2Reliability
If the field plate extension is increased to improve electrical isolation and reduce source-substrate coupling, then the specific-on resistance is reduced, but the device complexity and manufacturing difficulty increase
Solution Approach 1:
The field plate extension serves multiple functions simultaneously: it provides electrical isolation between the source and substrate, reduces source-substrate coupling, extends the drift region for higher breakdown voltage, and reduces the specific-on resistance by providing an additional current path. This multi-functionality allows a single structural modification to address multiple performance parameters without proportionally increasing device complexity.
Solution Approach 2:
The field plate extension acts as an intermediary structure that mediates between the source region and the substrate, providing controlled electrical isolation while maintaining necessary electrical connections. It serves as a intermediate conductive element that manages the electric field distribution and coupling between regions that would otherwise be directly interacting.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables a high-voltage LDMOS transistor with a breakdown voltage greater than 600V and minimized drain-source specific-on resistance, effectively addressing the limitations of existing LDMOS transistors by optimizing the dielectric layer thickness and field plate extension for improved electrical performance.
Implementation Method 1
incorporates a buried oxide layer and a field plate to enhance the reduced surface field (RESURF) effect
Implementation Method 2
reduce metal component of the drain-to-source on-resistance
Data Source
AI summary
A method includes forming a transistor device on a first side of a semiconductor-on-insulator structure. The semiconductor-on-insulator structure includes a substrate, a dielectric layer, and a buried layer between the substrate and the dielectric layer. The method also includes forming a conductive plug through the semiconductor-on-insulator structure. The conductive plug is in electrical connection with the transistor device. The method further includes forming a field plate on a second side of the semiconductor-on-insulator structure, where the field plate is in electrical connection with the conductive plug. The transistor device could have a breakdown voltage of at least 600V, and the field plate could extend along at least 40% of a length of the transistor device.