LDMOS Transistor Gate Dielectric Segmentation for Fast Switching
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Solution Overview
Problem
Conventional techniques for reducing gate to drain capacitance (Cgd) in LD transistors result in increased drain-to-source on-resistance, which decreases switching speed, making it difficult to achieve fast switching speeds while maintaining low Cgd.
Innovation Solution
The method involves forming a semiconductor device with a substrate having a device region defined by a source, gate, and drain, where a drift well with first polarity type dopants underlaps a portion of the gate, and a secondary portion with neutral dopants underlaps another portion of the gate, with a hybrid gate dielectric having different thicknesses to optimize switching speed and capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional techniques are used to reduce gate to drain capacitance, then Cgd is reduced, but drain-to-source on-resistance increases and switching speed decreases
Solution Approach 1:
The drift well is segmented into multiple regions with different dopant concentrations: a first region with higher dopant concentration and a second region with lower dopant concentration. This segmentation allows different portions of the drift well to serve different functions - the higher concentration region reduces capacitance while the lower concentration region maintains conductivity for fast switching.
Solution Approach 2:
Different regions of the drift well are assigned different local qualities through varying dopant concentrations. The first region has higher dopant concentration optimized for reducing gate-to-drain capacitance, while the second region has lower dopant concentration optimized for maintaining low on-resistance and fast switching speed.
2Reliability
If drift well structure is optimized for low Cgd, then breakdown voltage is improved, but switching speed may be compromised
Solution Approach 1:
The drift well is divided into segmented regions with different dopant concentrations to simultaneously achieve high breakdown voltage and fast switching. The first region with higher concentration provides voltage blocking capability while the second region with lower concentration enables fast carrier transport.
Solution Approach 2:
The dopant concentration parameter is changed across different regions of the drift well. By varying this parameter spatially - higher concentration in the first region for voltage breakdown control and lower concentration in the second region for speed optimization - both reliability and speed requirements are satisfied.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables faster switching speeds while maintaining low gate to drain capacitance and higher breakdown voltage, improving the reliability and performance of high power devices like LDMOS transistors.
Implementation Method 1
forming a drift well with first polarity type dopants in the substrate adjacent to a second side of the gate. The drift well underlaps a portion of the gate with a first edge of the drift well beneath the gate. The method also includes forming a secondary portion having neutral dopants in the drift well
Implementation Method 2
A gate dielectric of the gate comprises a first portion having a first thickness and a second portion having a second thickness, the second portion is over the secondary portion
Data Source
AI summary
A method of forming a device is disclosed. A substrate having a device region is provided. The device region comprises a source region, a gate and a drain region defined thereon. A drift well is formed in the substrate adjacent to a second side of the gate. The drift well underlaps a portion of the gate with a first edge of the drift well beneath the gate. A secondary portion is formed in the drift well. The secondary portion underlaps a portion of the gate with a first edge of the secondary portion beneath the gate. The first edge of the secondary portion is offset from the first edge of the drift well. A gate dielectric of the gate comprises a first portion having a first thickness and a second portion having a second thickness. The second portion is over the secondary portion.