LDMOS Gate Dielectric Thickness Variation
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Solution Overview
Problem
High-voltage LDMOS devices face gate oxide breakdown due to direct high voltage application in the drain-gate overlap region, leading to device failure, and increasing gate dielectric thickness degrades device performance.
Innovation Solution
A semiconductor device with a gate dielectric layer having a thicker first portion between the drain and gate, and a thinner second portion, allowing for higher breakdown voltage while maintaining device performance, achieved through a manufacturing method involving multiple gate dielectric layers with specific thickness ranges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the thickness of the gate dielectric layer is increased to raise the break-down voltage of the drain-gate overlap region, then the breakdown voltage is improved, but the device performance is degraded
Solution Approach 1:
The patent applies different thicknesses of gate dielectric layer to different regions: a first thickness in the drain-gate overlap region for high breakdown voltage, and a second thickness in other regions for optimal device performance. This local differentiation resolves the contradiction by tailoring the dielectric thickness to the specific functional requirements of each region.
Solution Approach 2:
The gate dielectric layer is segmented into multiple portions with different thicknesses - a first portion with greater thickness in the overlap region and a second portion with lesser thickness elsewhere. This segmentation allows each portion to independently optimize for its specific function, resolving the trade-off between breakdown voltage and device performance.
2Reliability
If a uniform thick gate dielectric layer is used to prevent gate oxide breakdown, then the breakdown voltage is improved, but the device performance is degraded
Solution Approach 1:
Instead of using a uniform thick gate dielectric layer throughout, the patent employs local quality by making the dielectric layer thicker only in the drain-gate overlap region where breakdown occurs, while maintaining a thinner thickness in other regions to preserve device performance characteristics.
Solution Approach 2:
The gate dielectric layer is divided into segments with different thicknesses - a first segment covering the overlap region with greater thickness for breakdown protection, and a second segment in other areas with lesser thickness for performance optimization.
Data Source
AI summary
A semiconductor device and its manufacturing method are disclosed. The semiconductor device comprises a gate, and source and drain regions on opposite sides of the gate, wherein a portion of a gate dielectric layer located above the channel region is thinner than a portion of the gate dielectric layer located at the overlap region of the drain and the gate. The thicker first thickness portion may ensure that the device can endure a higher voltage at the drain to gate region, while the thinner second thickness portion may ensure excellent performance of the device.