LDMOS Gate Structure for Hot-Carrier Degradation Suppression
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Solution Overview
Problem
Laterally diffused MOSFETs (LDMOSFETs) suffer from hot-carrier degradation due to large electric fields, leading to interface trap generation at the Si/SiO2 interface, which degrades electrical parameters and limits device lifetime.
Innovation Solution
The introduction of a healing gate structure, which applies a healing field to reverse the stress field during hot-carrier instability, suppressing impact ionization and de-trapping HCI-induced charges in the gate dielectric, thereby improving stability against hot-carrier instability without increasing channel length.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a conventional LDMOSFET structure is used, then high breakdown voltage is achieved, but hot-carrier degradation occurs due to large electric fields causing interface trap generation
Solution Approach 1:
The device is divided into two separate gate structures: a first gate structure for controlling the channel and a second gate structure (healing gate) for suppressing hot-carrier degradation. This segmentation allows independent optimization of breakdown voltage control and reliability enhancement without compromising either function.
Solution Approach 2:
A second gate structure acts as an intermediary element between the channel and the drain region. This healing gate structure suppresses impact ionization and hot-carrier generation by controlling the electric field distribution in the drift region, thereby protecting the Si/SiO2 interface from trap generation while maintaining high breakdown voltage.
2Reliability
If channel length is increased to reduce hot-carrier instability, then device reliability improves, but device complexity and area increase
Solution Approach 1:
The gate control function is segmented into two separate gate structures with distinct roles. The first gate structure maintains the original channel length for high-frequency performance, while the second gate structure (extending into the drift region) provides hot-carrier suppression without requiring channel length extension, thus avoiding increased device area and complexity.
Solution Approach 2:
Instead of extending the channel length in the horizontal dimension, the solution introduces a vertical dimension by extending the second gate structure into the drift region below the Si/SiO2 interface. This dimensional transition allows hot-carrier suppression without compromising channel length or increasing device footprint.
3Strength
If electric field strength is increased to improve breakdown voltage, then high-voltage capability is achieved, but impact ionization and HCI-induced charge generation increase
Solution Approach 1:
The second gate structure serves as an intermediary that modulates the electric field distribution in the drift region. By applying appropriate voltage to this healing gate, the peak electric field strength is reduced, suppressing impact ionization and hot-carrier generation while maintaining the overall high breakdown voltage capability of the device.
Solution Approach 2:
The electric field distribution parameter is dynamically controlled by the second gate structure. By adjusting the voltage applied to the healing gate, the peak electric field in the drift region can be optimized to suppress impact ionization while maintaining adequate breakdown voltage, thus changing the field distribution parameter to eliminate harmful effects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The healing gate effectively reduces HCI-induced current degradation by up to 35% and decreases substrate current, enhancing the device's reliability in high-voltage applications while preventing breakdown issues.
Implementation Method 1
applies a healing field to reverse the stress field during hot-carrier instability
Implementation Method 2
suppressing impact ionization
Data Source
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AI summary
A semiconductor device structure is provided. A first well region with a first type of conductivity is formed over a semiconductor substrate. A second well region with a second type of conductivity is formed over the semiconductor substrate. A well region is formed over the semiconductor substrate and between the first and second well regions. A first gate structure is disposed on the well region and partially over the first and second well regions. A drain region is in the first well region. A source region and a bulk region are in the second well region. The drain region, the source region and the bulk region have the first type of conductivity. A second gate structure is disposed on the second well region, and separated from the first gate structure by the source region and the bulk region.