LDMOS Gate Plate Segmentation for Low Resistance Switching
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Solution Overview
Problem
Conventional high-voltage semiconductor devices, such as LDMOS, face challenges with high gate resistance, leading to non-uniform switching and increased switching loss, especially when operating at high frequencies and high currents, due to the limitations of poly silicide formation and the inability to reduce gate resistance without increasing device size.
Innovation Solution
The introduction of a first gate plate formed by dividing the source field plate, electrically connected in parallel to the gate, which reduces gate resistance without adding extra metallization layers, ensuring uniform device turn-on and reducing switching loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the gate width is enlarged to increase current for high-frequency switching, then the current capability is improved, but the gate resistance increases and uniform turn-on is compromised
Solution Approach 1:
The gate electrode is divided into multiple segments (first gate electrode, second gate electrode, third gate electrode) arranged in parallel. This segmentation reduces the equivalent gate resistance while maintaining the required current capability for high-frequency switching operations.
Solution Approach 2:
A conductive layer is introduced as an intermediary component to connect the multiple gate electrode segments. This conductive layer serves as a mediator that equalizes the potential distribution across the gate, ensuring uniform turn-on while maintaining low equivalent resistance.
2Reliability
If multiple gate contacts are used to decrease gate resistance, then the gate resistance is reduced, but the device size increases due to extra metal routing area
Solution Approach 1:
Multiple gate electrode segments are merged into a unified structure that shares a common conductive layer. This merging approach reduces the total metal routing area compared to using separate gate contacts, thereby decreasing device size while maintaining low gate resistance.
Solution Approach 2:
The gate electrode structure extends in the lateral dimension with multiple segments arranged parallel to each other. This dimensional arrangement reduces the equivalent resistance without requiring additional vertical metal routing layers, thus avoiding increased device size.
3Reliability
If poly silicide is formed on polysilicon to decrease gate resistance, then the gate resistance is reduced, but it is insufficient for high-frequency high-current applications
Solution Approach 1:
The gate structure uses a composite configuration combining multiple gate electrode segments with a conductive layer, creating an equivalent gate resistance that is lower than what can be achieved with poly silicide formation alone. This composite approach enables high-frequency high-current switching performance.
Data Source
AI summary
An LDMOS includes a body region disposed in the substrate and having a first conductivity type; a drift region disposed in the substrate and having a second conductivity type; a source region disposed in the body region and having the second conductivity type; a drain region disposed in the drift region and having the second conductivity type; an isolation region disposed in the drift region between the source region and the drain region; a gate disposed on the body region and the drift region; a source field plate electrically connected to the source region; a drain field plate electrically connected to the drain region; and a first gate plate electrically connected to the gate. The first gate plate is correspondingly disposed above the gate. The shapes of the first gate plate and the gate are substantially the same when viewed from a top view.