LDMOS Gate Stack Layout for Lower Gate Charge and Higher Breakdown
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Solution Overview
Problem
Lateral double-diffused metal oxide semiconductor (LDMOS) transistors in switching regulators face limitations in high-frequency applications due to large gate charge and overlap between the gate and drain regions, which affect their voltage withstanding performance and efficiency.
Innovation Solution
The design includes a base layer with a source and drain region, a first dielectric layer adjacent to the source, a voltage withstanding layer between the dielectric and drain, and spatially isolated first and second conductors, where the juncture region is covered by one of the conductors, reducing gate charge and enhancing voltage withstanding performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the gate and drain regions are overlapped in conventional LDMOS transistors, then the manufacturing process is simplified, but the gate charge increases and voltage withstanding performance deteriorates
Solution Approach 1:
The gate electrode is divided into two separate electrodes: a first gate electrode positioned over the source region and a second gate electrode positioned over the drain region. This segmentation eliminates the overlap between gate and drain while maintaining manufacturing feasibility through sequential formation processes.
Solution Approach 2:
The patent introduces a vertical stacking arrangement where the first gate electrode is positioned at a first height and the second gate electrode is positioned at a second height, creating a three-dimensional configuration that separates the gate functions spatially without requiring lateral overlap.
2Reliability
If the gate and drain regions are separated to reduce gate charge, then voltage withstanding performance improves, but the device complexity increases
Solution Approach 1:
The first and second gate electrodes serve multiple functions: they individually control the source and drain regions, collectively form the gate stack, and the insulating layer between them provides both electrical isolation and structural support, reducing the need for additional components.
Solution Approach 2:
The first gate electrode, second gate electrode, and insulating layer are combined into an integrated gate stack structure that functions as a unified component, simplifying the overall device architecture while achieving the separation benefits.
Data Source
AI summary
A laterally diffused metal oxide semiconductor structure can include: a base layer; a source region and a drain region located in the base layer; first dielectric layer located on a top surface of the base layer and adjacent to the source region; a voltage withstanding layer located on the top surface of the base layer and located between the first dielectric layer and the drain region; a first conductor at least partially located on the first dielectric layer; and a second conductor at least partially located on the voltage withstanding layer, where the first and second conductors are spatially isolated, and a juncture region of the first dielectric layer and the voltage withstanding layer is covered by one of the first and second conductors.