LDMOS Gate Stack Layout for Adjustable Breakdown Voltage
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Solution Overview
Problem
Current LDMOS transistors face challenges in adjusting breakdown voltage effectively, limiting their flexibility in high-voltage applications due to fixed resistance characteristics.
Innovation Solution
The implementation of a dummy gate stack electrically coupled to a variable voltage allows for adjustable resistance in the LDMOS transistor, enabling flexible breakdown voltage settings by overlapping the active and dummy gate stacks with different regions of the transistor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate poly-silicon is extended to overlap with the drift region to increase breakdown voltage, then the breakdown voltage is maintained, but the resistance characteristics become fixed and inflexible
Solution Approach 1:
The gate structure is segmented into two independent parts: the active gate stack (first gate stack) that controls the main channel, and the dummy gate stack (second gate stack) that functions as an adjustable field plate. By separating these functions into distinct segments, the patent enables independent control of each component, allowing the dummy gate to provide adjustable resistance characteristics while the active gate maintains breakdown voltage through its overlap with the drift region.
Solution Approach 2:
The dummy gate stack is electrically coupled to a variable voltage source, transforming the static field plate structure into a dynamic component. By varying the voltage applied to the dummy gate stack, the resistance characteristics of the LDMOS transistor can be adjusted in real-time, enabling adaptive control of breakdown voltage and resistance without requiring physical structural changes.
2Device complexity
If a fixed overlap structure is used to maintain breakdown voltage, then the transistor structure is simple, but the transistor cannot accommodate different design demands for variable resistance
Solution Approach 1:
The gate poly-silicon is divided into two separate gate stacks with distinct functions. The first gate stack (active gate) maintains the necessary overlap with the drift region for breakdown voltage, while the second gate stack (dummy gate) is positioned and biased to provide adjustable resistance. This segmentation allows the structure to remain relatively simple while gaining significant functional flexibility.
Solution Approach 2:
The dummy gate stack serves multiple functions: it acts as an additional field plate to enhance breakdown voltage control, provides adjustable resistance characteristics, and can be used to fine-tune the electrical characteristics of the transistor for different application requirements. This multi-functionality allows a single structure to address multiple design demands without requiring separate components.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution allows for adjustable breakdown voltage, enhancing the transistor's performance in high-voltage applications by making the resistance variable, thus accommodating different design demands.
Implementation Method 1
The implementation of a dummy gate stack electrically coupled to a variable voltage allows for adjustable resistance in the LDMOS transistor, enabling flexible breakdown voltage settings
Data Source
AI summary
A MOS transistor includes a substrate, a first region, a second region, a source region, a drain region, an active gate stack, and a dummy gate stack. The substrate has a first conductivity. The first region having the first conductivity is formed in the substrate. The second region having a second conductivity is formed in the substrate and is adjacent to the first region. The source region with the second conductivity is formed in the first region. The drain region with the second conductivity is formed in the second region. The active gate stack is disposed on the first region. The dummy gate stack is disposed on the second region, and the dummy gate stack is electrically coupled to a variable voltage.