LDMOS Hot Carrier Suppression via Third Diffusion Region
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In semiconductor devices with LDMOS, the high electric field intensity near the trench insulating region leads to hot carrier generation, causing breakdown of the gate insulating film due to defects and carrier injection, especially from the difference in thermal expansion coefficients between the silicon substrate and the insulating film.
Innovation Solution
A semiconductor device design that includes a third diffusion region opposite in polarity to the first diffusion region, formed next to the side wall of the trench insulating region, which preforms a depletion layer to reduce electric field intensity and acts as an electric barrier to prevent hot carrier injection into the gate insulating film.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a trench insulating region is formed next to the drain contact region in the p-type diffusion region, then the withstand voltage of the LDMOS is improved, but the electric field intensity increases in the vicinity of the side wall of the trench insulating region, leading to hot carrier generation and gate insulating film breakdown
Solution Approach 1:
A third diffusion region of the second conductivity type is introduced as an intermediary structure between the p-type diffusion region and the trench insulating region. This third diffusion region acts as a mediator that modifies the electric field distribution, preventing direct interaction between the high electric field near the trench and the gate insulating film, thereby suppressing hot carrier generation while maintaining the withstand voltage improvement provided by the trench insulating region.
Solution Approach 2:
The third diffusion region is specifically positioned next to the side wall of the trench insulating region on the source contact region side, creating a localized modification of the electric field characteristics in the critical area. This local structural adjustment针对性地 addresses the hot carrier generation problem at the trench side wall without affecting the overall withstand voltage performance of the LDMOS device.
2Ease of operation
If the gate electrode covers from the end portion of the p-type source contact region to the top of the trench insulating region, then the gate control is improved, but carriers are attracted to the gate electrode and injected into the gate insulating film, causing breakdown
Solution Approach 1:
The third diffusion region serves as an intermediary barrier that intercepts carriers before they can be attracted to and injected into the gate insulating film. By positioning this diffusion region adjacent to the trench insulating region side wall, it creates an additional protective layer that prevents the harmful carrier injection while allowing the gate electrode to maintain its extended coverage for improved gate control.
3Manufacturing precision
If shallow trench isolation is used for element isolation, then the manufacturing precision is improved, but defects due to thermal expansion coefficient difference between silicon substrate and insulating film are generated in the vicinity of trench side walls
Solution Approach 1:
The third diffusion region is strategically positioned next to the trench insulating region side wall to serve as an intermediary protective structure. This diffusion region absorbs or deflects the harmful effects originating from the thermal expansion mismatch defects in the gate insulating film, preventing these defects from leading to device failure while maintaining the manufacturing precision benefits of shallow trench isolation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively suppresses hot carrier generation and prevents breakdown of the gate insulating film by reducing electric field intensity and creating an electric barrier to divert hot carriers away from vulnerable areas in the gate insulating film.
Implementation Method 1
a third diffusion region of a second conductivity type formed next to a side wall of the trench insulating region on the source contact region side in the first diffusion region between the source contact region and the trench insulating region
Implementation Method 2
Impact ionization consequently occurs in the vicinity of the side wall, and undesirably increases the possibility of hot carrier generation
Data Source
AI summary
A first diffusion region of a first conductivity type and a second diffusion region of a second conductivity type are formed next to each other in a semiconductor substrate. Drain and source contact regions of the first conductivity type are formed in the first and second diffusion region, respectively. A trench insulating region is formed in the first diffusion region between the drain and source contact regions. A third diffusion region of the second conductivity type is formed next to a side wall of the trench insulating region on the source contact region side in the first diffusion region between the source contact region and the trench insulating region. A gate electrode is formed on the semiconductor substrate through a gate insulating film to cover an area from an end portion of the source contact region to at least a part of a top surface of the trench insulating region.