LDMOS Punch-Through Prevention via Impurity Grading
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Solution Overview
Problem
Lateral diffusion MOS transistors (LDMOS) face a challenge in maintaining high breakdown voltage without increasing chip size, as lower impurity concentrations in the n-type well region can lead to punch-through, necessitating larger device sizes and higher costs.
Innovation Solution
A semiconductor device design that includes a well region of a second conductivity type with a base region and punch-through prevention regions of higher impurity concentration, along with a drift region and carrier supply and reception regions, to prevent punch-through and maintain breakdown voltage without increasing chip size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the distance between the drain region and the semiconductor substrate is increased to prevent punch-through, then punch-through is prevented, but the chip size increases leading to increased cost
Solution Approach 1:
The patent uses local quality by concentrating higher impurity concentration in specific punch-through prevention regions rather than uniformly increasing the distance between drain region and substrate. This localized structural modification prevents punch-through without requiring increased overall device area, thus resolving the contradiction between reliability and chip size.
Solution Approach 2:
The patent addresses the spatial constraint by introducing a vertical dimension solution - modifying impurity concentration distribution in the vertical profile of the n-type well region through punch-through prevention regions. This vertical parameter adjustment prevents punch-through without requiring horizontal expansion of chip area, resolving the contradiction between breakdown voltage and chip size.
Data Source
AI summary
A semiconductor device includes: a semiconductor layer of a first conductivity-type; a well region of a second conductivity-type provided at an upper part of the semiconductor layer; a base region of the second conductivity-type provided at an upper part of the well region; a carrier supply region of the first conductivity-type provided at an upper part of the base region; a drift region of the first conductivity-type provided separately from the base region; a carrier reception region of the first conductivity-type provided at an upper part of the drift region; a gate electrode provided on a top surface of the well region interposed between the base region and the drift region via a gate insulating film; and a punch-through prevention region of the second conductivity-type provided at the upper part of the well region and having an impurity concentration different from the impurity concentration of the base region.