LDMOS Transistors With Split Gate Reducing Breakdown Voltage
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Solution Overview
Problem
LDMOS transistors experience breakdown due to high drain to source voltage, primarily caused by impact ionization at the corner of the gate and shallow trench isolation, leading to increased electric fields, which existing methods attempt to mitigate by lengthening the drift region or reducing implants, both of which increase on-resistance.
Innovation Solution
The design incorporates a split gate structure with a separation space over the drift region and isolation region, reducing the high electric field effect while maintaining a lower on-resistance, by separating the gate structure into two portions with a gap that can be filled with SiN or ILD, and forming a drift region with portions under and adjacent to the isolation region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the length of the drift region is increased to reduce the electric field effect, then the breakdown voltage is improved, but the on resistance increases
Solution Approach 1:
The gate structure is divided into two separate gates with a gap between them, positioned over different portions of the drift region. This segmentation allows independent control of electric field distribution in different areas, reducing the peak electric field at critical corners while maintaining better overall resistance characteristics compared to a single long drift region approach.
Solution Approach 2:
The split gate structure creates different electric field conditions in different local regions of the drift region. The first gate covers one portion while the second gate covers another portion, allowing localized optimization of the electric field distribution to reduce impact ionization at corners while maintaining lower on-resistance overall.
2Reliability
If the dosage of implants into the drift region is reduced to reduce the electric field effect, then the breakdown voltage is improved, but the on resistance increases
Solution Approach 1:
The implantation process is segmented into multiple regions under different gates. By controlling implants separately in regions under the first gate versus regions under the second gate, the dosage can be optimized locally to reduce peak electric fields without requiring a uniform reduction across the entire drift region, thereby maintaining lower on-resistance.
3Device complexity
If the gate structure is made continuous to simplify manufacturing, then the device complexity is reduced, but the electric field distribution becomes less controllable
Solution Approach 1:
The gate structure is intentionally segmented into two separate gates with a gap, creating distinct control zones over different portions of the drift region. This segmentation provides superior control over electric field distribution compared to a continuous gate, allowing independent optimization of field conditions in different areas to prevent breakdown.
Solution Approach 2:
The gap between the two gates acts as an intermediary region that allows different electric field conditions to exist on either side. This gap can be filled with dielectric material or left as a void, serving as a mediator that enables independent control of the electric field in regions under each gate, improving overall reliability.
Data Source
AI summary
A transistor including a source region, drain region, channel region, drift region, isolation region, a first gate structure over the channel region, and a second gate structure over the isolation region is provided. The drift region includes a first portion located under the isolation region and a second portion located laterally adjacent to the isolation region. The first gate structure is separated by a first separation space from the second gate structure. The first separation space is located over a portion of the second portion of the drift region and a portion of the isolation region.