LDMOS Transistor Stepped Oxide Charge Balance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High power LDMOS transistors in BCD fabrication processes face reduced electrical breakdown voltage and increased resistance due to deviations in charge balance and electrostatics caused by shallow trench isolation and reduced surface field implants, particularly affecting performance in low voltage applications up to 60 volts.
Innovation Solution
Incorporating a stepped oxide region with substantial uniform thickness and deep p-type doping, along with shallow n-type doping, to maintain charge balance and minimize penetration, thereby optimizing the device area and reducing resistance while preserving electrostatic profiles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If shallow trench isolation (STI) regions are located between the fingers of an LDMOS transistor, then device isolation and structural definition are achieved, but charge balance and electrostatics deviate from optimum, reducing electrical breakdown voltage
Solution Approach 1:
The patent removes STI regions from between the LDMOS transistor fingers, extracting the problematic isolation structure that caused charge balance deviation. By eliminating these intermediate STI regions, the invention restores optimal charge balance and electrostatic characteristics while maintaining device isolation through alternative means, directly resolving the contradiction between structural definition and electrical performance.
Solution Approach 2:
The patent segments the device structure by separating the active finger region from isolation structures, allowing the fingers to be closely spaced without intervening STI regions. This segmentation enables independent optimization of the active region for charge balance while using peripheral isolation structures for device definition, thus resolving the conflict between isolation requirements and electrostatic optimization.
2Reliability
If RESURF implants are used to achieve low on-resistance and high voltage breakdown, then power switch performance improves, but performance deteriorates in low voltage applications up to around 60 volts due to charge balance deviations
Solution Approach 1:
The patent applies local quality by implementing different isolation configurations for different voltage regimes. By removing STI regions between fingers specifically针对低电压应用, the invention optimizes charge balance for low voltage operation (up to 60V) while maintaining the ability to achieve high voltage breakdown through proper RESURF implant design in other regions, thus resolving the adaptability contradiction.
3Ease of manufacture
If oxide regions penetrate the silicon surface (such as STI), then device isolation is achieved, but LDMOS transistor reliability reduces due to trap creation and slowed transistor response
Solution Approach 1:
The patent extracts oxide penetration regions from between the transistor fingers, eliminating the source of trap creation that degraded reliability. By removing these penetrating oxide structures from critical areas, the invention prevents trap formation and maintains fast transistor response while preserving necessary device isolation through alternative isolation schemes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively enhances the breakdown voltage and reduces resistance in LDMOS transistors, improving the overall performance and reliability of high power switches, particularly in DC to DC power converters.
Implementation Method 1
maintain charge balance and minimize penetration, thereby optimizing the device area and reducing resistance while preserving electrostatic profiles
Implementation Method 2
Incorporating a stepped oxide region with substantial uniform thickness and deep p-type doping, along with shallow n-type doping, to maintain charge balance
Data Source
AI summary
A LDMOS transistor that may include (i) a first region that is a reduced surface field (RESURF) implant region of a first type; (ii) a second region that is a RESURF implant region of a second type, wherein the first type differs from the second type; (iii) a gate; (iv) a stepped oxide region and a gate oxide region that are positioned above the first region and below the gate. Each one of the first region and the second region has a substantially uniform thickness