LDMOS Stress Layer Tuning for Balanced N/P Channel Performance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing manufacturing processes for LDMOS integrated devices struggle to simultaneously achieve optimal performance for both N-channel and P-channel devices, as the introduction of stress materials like SiN improves RESURF capability for N-channel devices but degrades P-channel device performance, making it challenging to produce high-performance devices for both channels in the same process flow.
Innovation Solution
A manufacturing method that involves forming a semiconductor substrate with distinct dielectric and stress material layers for N-channel and P-channel areas, where the thickness and stress of these layers are optimized to enhance electron mobility and RESURF capability, allowing for the simultaneous improvement of both N-channel and P-channel device performance by adjusting the dielectric layer thickness and applying heat treatment to the stress material layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the same process flow is used for both N-channel and P-channel devices, then manufacturing simplicity is maintained, but optimal performance for both device types cannot be achieved simultaneously
Solution Approach 1:
The patent implements a universal fabrication process flow that can produce both N-channel and P-channel devices using the same sequence of manufacturing steps. The process uses conditional formation of stress material layers based on device type, allowing a single process flow to serve multiple device configurations and achieve optimal performance for both channel types without requiring separate fabrication lines.
Solution Approach 2:
The patent changes material parameters (stress characteristics, composition, thickness) of the stress material layers based on the specific device type being fabricated. By adjusting these parameters conditionally within the same process flow, the method achieves optimized performance for both N-channel and P-channel devices while maintaining manufacturing simplicity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method improves the electron mobility and reduces on-resistance of both N-channel and P-channel devices, ensuring high-performance LDMOS integrated devices can be manufactured in the same process flow while maintaining effective RESURF capability, thus addressing the limitations of previous processes.
Implementation Method 1
performing a heat treatment to adjust a stress of the stress material layer and increase electron mobility of the device
Data Source
AI summary
In a manufacturing method for an LDMOS integrated device, a provided semiconductor substrate has an NLDMOS area and a PLDMOS area; then a dielectric layer on the NLDMOS area and a dielectric layer on the PLDMOS area are formed on the semiconductor substrate, and a stress material layer is formed on the dielectric layer on the NLDMOS area and/or on the dielectric layer on the PLDMOS area, the thickness of the dielectric layer on the NLDMOS region being greater than the thickness of the dielectric layer on the PLDMOS region; then heat treatment is performed to adjust the stress of the stress material layer, so as to improve the electron mobility of a device; then the stress material layer is removed.