LDMOS Transistor Two-Section Gate Reduces Capacitance
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Solution Overview
Problem
The increased capacitance due to the overlap of the gate with the drift region in MOS transistors reduces the maximum effective operating frequency of integrated circuits, particularly in LDMOS, DMOS, and DEMOS transistors, limiting their performance.
Innovation Solution
The MOS transistor design includes a gate formed in two sections, with at least half of the drift region not covered by the gate, and optionally connected by gate material, reducing gate-drain capacitance and allowing for higher operating drain voltage by separating the biasing of the gate sections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate overlaps the drift region to provide coverage, then the gate control is improved, but the gate-drain capacitance increases reducing maximum operating frequency
Solution Approach 1:
The gate is divided into two separate sections: a first gate section over the channel region and a second gate section over the drain insulator. This segmentation reduces the overlap between the gate and drift region, thereby reducing gate-drain capacitance and increasing maximum operating frequency while maintaining necessary gate control through the distributed gate structure.
Solution Approach 2:
The gate structure extends into a new spatial dimension by placing a second gate section over the drain insulator region. This dimensional extension allows the gate to provide control coverage without directly overlapping the drift region, effectively reducing capacitance while maintaining control functionality through three-dimensional gate distribution.
2Ease of manufacture
If the gate is formed as a single continuous structure, then the manufacturing is simpler, but the gate-drain capacitance is higher reducing performance
Solution Approach 1:
The gate is segmented into two distinct sections that can be formed using standard photolithography and deposition processes. The segmentation is achieved through pattern definition and selective deposition, which are routine manufacturing techniques, thus maintaining ease of manufacture while achieving the performance benefits of reduced gate-drain capacitance.
3Speed
If at least half of the drift region is not covered by the gate, then the gate-drain capacitance is reduced, but the gate control coverage is decreased
Solution Approach 1:
The gate control function is segmented and distributed: the first gate section provides control over the channel region while the second gate section provides control over the drain insulator region. This distributed segmentation ensures adequate gate control coverage is maintained even though the drift region is partially uncovered, enabling both high switching speed and reliable device operation.
Solution Approach 2:
Gate control coverage is maintained by extending control into a different spatial dimension - the second gate section is positioned over the drain insulator rather than directly over the drift region. This dimensional repositioning provides alternative control pathways that maintain reliability while reducing harmful capacitance effects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces gate-drain capacitance, enabling faster switching and higher drain voltage operation of the MOS transistors, thereby enhancing the performance of integrated circuits.
Implementation Method 1
the gate of the MOS transistor is formed in two sections; the first gate section is located over the channel region
Implementation Method 2
Capacitance due to overlap of the gate with the drift region increases a total gate capacitance
Data Source
AI summary
An integrated circuit containing an MOS transistor with a drain drift region adjacent to the channel region, a field oxide element in the drain region, a first gate section over the channel region and a second gate section over the field oxide element, with a gap between the gate sections so that at least half of the drift region is not covered by gate. A process of forming an integrated circuit containing an MOS transistor with a drain drift region adjacent to the channel region, a field oxide element in the drain region, a first gate section over the channel region and a second gate section over the field oxide element, with a gap between the gate sections so that at least half of the drift region is not covered by gate, so that the source/drain implant is blocked from the drift region below the gap.