LDMOS and VFET Integration on Shared Substrate
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Solution Overview
Problem
Conventional planar FETs have reached scaling limits, necessitating unconventional geometries to continue performance improvements in semiconductor devices, particularly in achieving longer gate lengths and larger dielectric spacers for vertical FinFETs while integrating with LDMOS devices on the same substrate.
Innovation Solution
The method involves forming both lateral and vertical device regions on a semiconductor substrate, with fin structures created using sidewall image transfer or photoresist etch mask processes, followed by dielectric layer formation, dopant implantation, and epitaxial semiconductor material growth to define source and drain regions for LDMOS and VFET devices, respectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional planar FET scaling is continued, then device density increases, but device performance improvements reach fundamental limits
Solution Approach 1:
The patent transitions from planar 2D FET geometry to vertical 3D FinFET geometry, utilizing the third dimension (vertical channel length perpendicular to substrate) to achieve longer gate lengths without increasing lateral footprint. This dimensional change allows continued performance improvement while maintaining high device density through vertical stacking.
2Reliability
If vertical FinFET geometry is adopted to achieve longer gate lengths, then device performance improves, but manufacturing complexity increases
Solution Approach 1:
The patent divides the substrate into separate lateral device region and vertical device region, allowing independent optimization and processing of LDMOS and VFET structures. This segmentation enables specialized manufacturing processes for each device type while sharing common substrate infrastructure, thereby managing overall manufacturing complexity.
Solution Approach 2:
The patent implements a shared substrate platform that supports both lateral LDMOS devices and vertical FinFET devices with different geometries and processing requirements. Common structures such as shared dielectric layers, fin formation processes, and substrate preparation provide universal functionality that reduces overall manufacturing complexity despite device diversity.
3Reliability
If vertical FinFET structures are formed with longer gate lengths, then device performance improves, but dielectric spacer dimensions must be increased
Solution Approach 1:
The patent utilizes vertical dielectric spacers extending perpendicular to the substrate surface to achieve the required spacer lengths for vertical FinFETs. By transitioning from lateral to vertical orientation, the dielectric spacers can provide sufficient dimensional coverage for gate control without increasing lateral device footprint, maintaining compatibility with integrated circuit layouts.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the integration of LDMOS and VFET devices with enhanced gate lengths and dielectric spacers, improving performance by allowing for longer gate heights and larger spacers, thus overcoming the scaling limitations of conventional planar FETs.
Implementation Method 1
An epitaxial semiconductor material is formed on the at least one first fin structure in the lateral device region of the substrate and the at least one second fin structure in the vertical device region of the substrate
Implementation Method 2
a dopant region is formed in the vertical device region of the substrate for the first of a source region and drain region
Data Source
AI summary
An electrical device that in some embodiments includes a substrate including a lateral device region and a vertical device region. A lateral diffusion metal oxide semiconductor (LDMOS) device may be present in the lateral device region, wherein a drift region of the LDMOS device has a length that is parallel to an upper surface of the substrate in which the LDMOS device is formed. A vertical field effect transistor (VFET) device may be present in the vertical device region, wherein a vertical channel of the VFET has a length that is perpendicular to said upper surface of the substrate, the VFET including a gate structure that is positioned around the vertical channel.