LDMOSFET Interconnect Structure for Electrical Coupling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor devices with LDMOS transistors face limitations in maximizing performance due to inefficiencies in interconnect line structures and coupling methods, which affect the electrical coupling and overall performance of unit MISFET elements.
Innovation Solution
The semiconductor device incorporates a specific interconnect line structure with multiple layers, where thinner first interconnect lines are used for source and gate connections, and thicker second interconnect lines for drain connections, along with conductive plugs in trenches to enhance electrical coupling between unit MISFET elements, improving performance by reducing resistance and optimizing breakdown voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If uniform thickness interconnect lines are used for all connections, then manufacturing simplicity is maintained, but electrical coupling performance and breakdown voltage are insufficient
Solution Approach 1:
The patent applies local quality by using interconnect lines with different thicknesses for different functional connections: thinner first interconnect lines for source and gate connections where lower resistance is critical, and thicker second interconnect lines for drain connections where higher current carrying capacity is needed. This localized differentiation optimizes electrical coupling performance for each specific connection type while maintaining overall manufacturing feasibility through a systematic multi-layer approach.
Solution Approach 2:
The patent transitions from a single-layer interconnect structure to a multi-layer structure with at least two interconnect line layers. This dimensional change allows for optimized electrical paths in both lateral and vertical dimensions, enabling better control over resistance and breakdown voltage characteristics while providing separate routing paths for different signal types (source, gate, drain connections).
2Reliability
If thicker interconnect lines are used for all connections, then resistance is reduced, but breakdown voltage capability deteriorates due to electric field concentration
Solution Approach 1:
The patent applies local quality by strategically assigning different interconnect line thicknesses to different connection types: thinner first interconnect lines are used for source and gate connections where maintaining high breakdown voltage is critical, while thicker second interconnect lines are used for drain connections where reducing resistance loss is the priority. This localized differentiation allows each connection to have optimized characteristics for its specific electrical requirements.
Solution Approach 2:
The patent introduces intermediate structures including insulating films between interconnect layers and conductive plugs in trenches to mediate the electrical connections. These intermediary elements help distribute electric fields more evenly, preventing concentration at thin interconnect regions while still achieving low resistance through the thicker drain interconnect lines.
3Productivity
If simple single-layer interconnect structure is used, then manufacturing is easier, but electrical coupling and performance optimization are limited
Solution Approach 1:
The patent introduces a multi-layer interconnect structure with at least two distinct interconnect line layers, adding a vertical dimension to the interconnect architecture. This enables optimized electrical coupling and performance by providing separate routing paths for different signals (source, gate, drain connections) with different thickness characteristics, while the systematic layering approach maintains manufacturing feasibility through established multi-layer fabrication processes.
Solution Approach 2:
The patent implements local quality by differentiating interconnect line thicknesses across different layers and connection types. The first interconnect layer uses thinner lines for source and gate connections, while the second layer uses thicker lines for drain connections. This localized optimization enhances device performance through improved electrical coupling and reduced resistance loss, while the regularized multi-layer structure keeps manufacturing complexity manageable.
Data Source
AI summary
Provided is a semiconductor device having improved performance. A semiconductor substrate is formed with unit LDMOSFET elements. The unit LDMOSFET elements have respective source regions electrically coupled to each other via a first source interconnect line and a second source interconnect line. The unit LDMOSFET elements have respective gate electrodes electrically coupled to each other via a first gate interconnect line and also electrically coupled to a second gate interconnect line in the same layer as that of the second source interconnect line via the first gate interconnect line. The unit LDMOSFET elements have respective drain regions electrically coupled to a back surface electrode via a conductive plug embedded in a trench of the semiconductor substrate. Each of the first source interconnect line and the first gate interconnect line has a thickness smaller than that of the second source interconnect line. Over the plug, the first gate interconnect line extends.