LDO Regulator Gate Drive Topology for Inrush Current Prevention

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Solution Overview

Problem

Existing low voltage drop output regulators (LDO regulators) suffer from inrush currents during initial operation, which can damage circuits due to high peak currents, and existing solutions to prevent this often require large circuit designs, increasing size and manufacturing costs.

Innovation Solution

A low voltage drop output regulator design incorporating a differential amplifier, a first MOS transistor, and an inrush preventer with a second MOS transistor and a switch in series, connected between the power voltage terminal and the drive node, to maintain a non-zero voltage level during the initial operation period, thereby preventing inrush currents.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a typical inrush preventer with multiple transistors, switches, and resistors is used, then inrush current is prevented, but the circuit design area increases significantly

Engineering Contradiction:
Improveinrush current preventionVSAvoidcircuit design area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent extracts only the essential functional elements needed for inrush current prevention, eliminating redundant components. The simplified inrush preventer uses merely a second MOS transistor and a switch, removing unnecessary resistors and additional transistors switches from the conventional design, thereby significantly reducing the circuit design area while maintaining inrush current prevention capability

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent merges the inrush prevention function with the existing differential amplifier and pass transistor structure. The second MOS transistor is integrated into the gate control path of the pass transistor, and the switch is combined with the amplifier enable signal logic, creating a unified control mechanism that prevents inrush current without requiring separate dedicated circuit blocks

Inventive Principle:
Principle #5Merging (Combining)

2Ease of manufacture

If the circuit design area is reduced with fewer components, then manufacturing cost decreases, but the ability to maintain voltage control during initial operation may be compromised

Engineering Contradiction:
Improvemanufacturing costVSAvoidvoltage control capability
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent changes the operational parameters of the remaining components to achieve effective inrush prevention. The second MOS transistor is configured with specific threshold voltage characteristics, and the switch timing is synchronized with the amplifier enable signal transitions, ensuring that voltage control is maintained during initial operation despite the reduced component count

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS12416933B2Low voltage drop output regulator for preventing inrush current and method for controlling thereof
Publication Date: 2025.09.16 MAGNACHIP SEMICON LTD
  • US12416933B2 patent drawing
  • US12416933B2 patent drawing
  • US12416933B2 patent drawing

AI summary

A low voltage drop output regulator and a method for controlling thereof for preventing an inrush current that occurs momentarily during an initial operation of a circuit are described. The low voltage drop output regulator includes a differential amplifier configured to output an amplified voltage by comparing a reference voltage with a feedback voltage, a first MOS transistor configured to output an output voltage to a drain terminal by receiving the amplified voltage in a gate terminal, and an inrush preventer connected between a power voltage terminal and a drive node to prevent the inrush current of the first MOS transistor during an initial operation period. The inrush preventer includes a determining unit and a limiter, and the limiter is configured only by a MOS transistor and a switch connected in series between a power voltage terminal and a drive node.