LDO Power Design With Preemptive Load-Switching PSRR Control

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Solution Overview

Problem

Conventional power designs for electronic devices experience significant drops in system voltage and LDO output voltage during load switching from light to heavy loads, leading to a poor power supply rejection ratio (PSRR) due to slow-response feedback control.

Innovation Solution

The implementation of a feedback control path that includes a flag signal asserted before the load current reaches a heavy load level, allowing the voltage regulator to pre-adjust the system voltage and LDO output voltage, thereby ensuring a stable power supply during load switching.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If conventional feedback control is used to detect changes in LDO output voltage or load current, then the system can compensate for voltage changes, but the response time is too slow causing significant voltage drops during load switching

Engineering Contradiction:
Improveresponse speed of feedback controlVSAvoidpower supply rejection ratio
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent applies preliminary action by detecting the load switching signal before the actual load current changes occur, and asserting the feedback control signal in advance. This allows the buck converter to pre-adjust the system voltage before the LDO voltage would drop, maintaining stable voltage output and good PSRR during the transition from light to heavy load conditions.

Inventive Principle:
Principle #10Preliminary action

2Device complexity

If the feedback control waits for voltage changes to occur before compensating, then the control logic is simple, but the system voltage and LDO output voltage significantly fall down before compensation takes effect

Engineering Contradiction:
Improvefeedback control logicVSAvoidvoltage stability during load switching
Core Design Contradiction:
Device complexityVSStability of the object's composition

Solution Approach 1:

The patent detects load switching signals in advance (before the actual load change occurs) and asserts the feedback control signal preemptively. This allows the voltage regulator to adjust system voltage before the LDO output voltage would drop, maintaining voltage stability without requiring complex control logic.

Inventive Principle:
Principle #10Preliminary action

3Ease of operation

If the buck converter adjusts system voltage after LDO voltage drops are detected, then the control mechanism is straightforward, but the voltage headroom becomes too small to maintain PSRR during the transition

Engineering Contradiction:
Improvecontrol mechanism simplicityVSAvoidpower supply rejection ratio
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The patent asserts the feedback control signal in advance by detecting load switching signals before they fully manifest as voltage drops. This preemptive control allows the buck converter to adjust system voltage ahead of time, maintaining adequate voltage headroom and PSRR without complicating the control mechanism.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20250181095A1Electronic device using a power design with improved power supply rejection ratio and method for operating the power design
Publication Date: 2025.06.05 MEDIATEK INC
  • US20250181095A1 patent drawing
  • US20250181095A1 patent drawing
  • US20250181095A1 patent drawing

AI summary

An electronic device using a power design with a good power supply rejection ratio (PSRR) is shown. The electronic device includes a voltage regulator, a low dropout regulator (LDO), an application, and a feedback control path. The voltage regulator generates a system voltage. The LDO is coupled to the voltage regulator to receive the system voltage for generation of an LDO output voltage. The application is coupled to the LDO to receive the LDO output voltage. The feedback control path couples a flag signal to the voltage regulator. In response to the flag signal being asserted, the voltage regulator pulls up the system voltage. The flag signal is asserted before the load current of the application reaches a heavy load current level.