LDO Circuit Zero Tuning for Intermediate-Frequency PSR
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Solution Overview
Problem
Existing communication terminals face interference issues due to intermediate frequency signals entering the radio frequency chip, which deteriorate performance and limit the development of radio frequency communication technologies.
Innovation Solution
An LDO circuit with a power supply rejection function, incorporating a bandgap reference module with an intermediate frequency zero adjustment unit and an amplifier module with an intermediate frequency zero generation unit, to enhance the capability of suppressing intermediate frequency signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a conventional LDO circuit is used to provide voltage bias to the radio frequency chip, then the radio frequency chip can operate with a stable voltage, but intermediate frequency signals generated by other components (CPU, memory chip, etc.) can enter the radio frequency chip through the power supply and interfere with its performance
Solution Approach 1:
The patent introduces an LDO circuit as an intermediary component between the power supply and the radio frequency chip. This LDO circuit specifically targets and filters intermediate frequency signals (100 KHz to 10 MHz) that would otherwise couple into the radio frequency chip through the power supply network, thereby protecting the chip from interference while maintaining stable voltage operation
Solution Approach 2:
The LDO circuit modifies the power supply parameters by dynamically adjusting its operation to reject specific frequency ranges (intermediate frequencies). By changing the operating parameters of the LDO to optimize power supply rejection ratio (PSR) at intermediate frequencies, the circuit effectively suppresses harmful signals while maintaining the necessary voltage stability for radio frequency operation
2Object-affected harmful factors
If the power supply capability to suppress intermediate frequency signals is enhanced, then radio frequency chip performance is improved, but the LDO circuit complexity increases due to the need for specialized intermediate frequency zero adjustment and generation units
Solution Approach 1:
The LDO circuit is designed to perform multiple functions: standard voltage regulation and specialized intermediate frequency rejection. By integrating intermediate frequency zero adjustment and generation units into the existing LDO architecture, the circuit achieves both general-purpose voltage biasing and specific frequency-range suppression without requiring completely separate circuits
Solution Approach 2:
The LDO circuit performs preliminary filtering and rejection of intermediate frequency signals before they can reach the radio frequency chip. The intermediate frequency zero generation unit proactively creates the necessary frequency characteristics to suppress harmful signals in advance, preventing interference rather than correcting it after it occurs
Data Source
AI summary
An LDO circuit having a power supply rejection function, a chip, and a communication terminal. The LDO circuit includes a bandgap reference module provided with an intermediate frequency zero adjustment unit, an amplification module provided with an intermediate frequency zero generation unit, and a power output module. The bandgap reference module is connected to the amplification module, and the amplification module is connected to the power output module. For the purpose of power supply rejection at an intermediate frequency, the intermediate frequency zero adjustment unit in the bandgap reference module and the intermediate frequency zero generation unit in the LDO circuit are adjusted in coordination to better optimize the intermediate frequency power supply rejection performance.