Bit-Interleaved LDPC Modulation for >100 Gb/s Optical Links
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Solution Overview
Problem
Current technologies face challenges in achieving high-speed optical transmission beyond 100 Gb/s using commercially available components, as electrically time-division multiplexed (ETDM) transceivers operating at 100 Gb/s are expensive and not widely available, necessitating alternative approaches for efficient data transmission.
Innovation Solution
The implementation of bit-interleaved low-density parity-check (LDPC)-coded modulation (BI-LDPC-CM) scheme combined with M-ary differential phase-shift keying (DPSK), utilizing identical LDPC encoders for multiple bit streams and iterative demapping and decoding to enhance spectral efficiency and bit-error rate performance, allowing for >100 Gb/s transmission with commercially available 40 Gb/s modulators and photodetectors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If electrically time-division multiplexed (ETDM) transceivers operating at 100 Gb/s are used, then transmission speed is improved, but device cost and complexity increase significantly
Solution Approach 1:
The patent segments the high-speed transmission task into multiple parallel lower-speed channels. Specifically, it uses multiple 40 Gb/s transceivers operating in parallel to achieve aggregate transmission rates of 100 Gb/s or higher, avoiding the need for expensive 100 Gb/s transceivers while maintaining high overall transmission speed
Solution Approach 2:
The patent transitions from a single high-speed channel to multiple parallel channels, adding a spatial dimension to the transmission system. By using multiple 40 Gb/s channels operating simultaneously, the system achieves 100 Gb/s aggregate throughput without requiring individual transceivers to operate at 100 Gb/s, thus reducing device complexity and cost
2Productivity
If bit-interleaved LDPC-coded modulation with M-ary DPSK is implemented, then spectral efficiency is improved, but decoding complexity increases
Solution Approach 1:
The patent segments the decoding process into iterative stages, using sequential decoding steps that process extrinsic information progressively. The LDPC decoder is divided into multiple processing stages that operate iteratively, where each stage refines the decoding results based on feedback from previous stages, managing complexity through structured iteration
Solution Approach 2:
The patent implements feedback mechanisms in the iterative decoding process, where extrinsic information from the LDPC decoder is fed back to the demapper and re-encoder. This feedback loop allows the system to progressively improve decoding accuracy through multiple iterations, achieving high spectral efficiency while managing complexity through controlled iterative refinement
Data Source
AI summary
A transmitter includes a plurality of encoders configured to receive source bit streams from m information sources, each of the plurality encoders including identical (n,k) low-density parity check (LDPC) codes of code rate r=k/n, where k is a number of information bits and n is codeword length. An interleaver is configured to collect m row-wise codewords from the plurality of encoders, and a mapper is configured to receive m bits at a time column-wise from the interleaver and to determine an M-ary signal constellation point. A modulator is configured to modulate a light source in accordance with the output of the mapper at a transmission rate Rs/r (Rs—the symbol rate, r—-the code rate). A receiver and transmission and receiving methods are also disclosed.