Lead Frame Ball Grid Array Traces Under Die
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Solution Overview
Problem
Current semiconductor packaging technologies face challenges in achieving high contact density and robustness due to the need for multiple etching and plating steps, which increase costs and reduce reliability, and they do not allow for routing traces under the die, limiting contact density and requiring additional steps for standoff formation.
Innovation Solution
A semiconductor package with routing traces under the die and standoffs formed by plating both sides of a copper substrate, where the routing traces act as both electrical pathways and thermal sinks, and the standoffs provide a robust connection to the PCB, allowing for increased contact density and reduced manufacturing steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple etching and plating steps are used to form contacts and standoffs, then contact robustness can be improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent combines the formation of contacts and standoffs into a single plating step. The copper substrate is selectively plated on both sides to form die attach pads and contacts, while the unetched copper regions between plated areas automatically form standoffs. This eliminates the need for separate etching and plating steps that were previously required, thereby reducing manufacturing complexity while maintaining contact robustness through the integrated plated structure.
Solution Approach 2:
The copper substrate serves multiple functions simultaneously: it provides the base material for plated contacts, forms standoffs through selective etching, and creates routing traces. The single plating process accomplishes what previously required multiple separate processes, making the manufacturing system more efficient and less complex while producing equally robust electrical connections.
2Quantity of substance
If contact density is increased to meet higher I/O requirements, then package functionality is improved, but package robustness deteriorates due to thinner plating
Solution Approach 1:
The patent routes traces underneath the die in the vertical dimension, allowing contacts to be positioned around the periphery of the die attach pad. This three-dimensional arrangement of traces (under the die) combined with peripheral contacts enables high contact density without requiring excessively thin plating, as the plated structures maintain adequate thickness for robustness while achieving high I/O counts through spatial optimization.
3Ease of operation
If standoffs are added as separate components to provide spacing, then ease of mounting is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent integrates standoffs into the leadframe structure itself by leaving unetched copper regions between the plated contact areas. These integrated standoffs provide the necessary spacing and mounting features without requiring separate standoff components or additional assembly steps. The single plating and etching process simultaneously creates both the electrical contacts and the mechanical standoffs, eliminating separate component assembly.
4Quantity of substance
If traces are routed under the die, then contact density is improved, but manufacturing complexity increases due to additional process steps
Solution Approach 1:
The routing traces are formed as integral parts of the leadframe structure before die attachment. The copper substrate is selectively plated and etched to create the trace patterns that will route signals underneath the die. By preparing these trace pathways in advance during the leadframe fabrication process, the patent enables high contact density without adding complexity to the subsequent die assembly process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables a more robust and cost-effective semiconductor package with increased contact density and thermal management capabilities, while maintaining a thin form factor and reducing the likelihood of peeling issues, by using a streamlined process that requires fewer manufacturing steps.
Implementation Method 1
plating both sides of a copper substrate to form die attach pads and contacts
Implementation Method 2
the routing traces act as both electrical pathways and thermal sinks
Data Source
AI summary
A package includes a first plated area, a second plated area, a die attached to the first plated area, and a bond coupling the die to the second plated area. The package further includes a molding encapsulating the die, the bond, and the top surfaces of the first and second plated areas, such that the bottom surfaces of the first and second plated areas are exposed exterior to the package. Additional embodiments include a method of making the package.