Leadframe Dual-Face Package Without Through-Silicon Vias
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Solution Overview
Problem
Conventional dual-face packages require through-silicon via technology, which involves high-temperature treatment and is difficult to apply in semiconductor packaging, limiting their use due to the complexity of forming and insulating through holes in semiconductor substrates.
Innovation Solution
A leadframe-type dual-face package is developed where an LSI chip is sealed with mold resin and has electrodes on both faces, with inner lead portions connected by wiring and bump electrodes formed on the leadframe, allowing for external connections without the need for through-silicon vias, enabling the use of ordinary leadframe technology and reducing manufacturing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If through-silicon via technology is used to create dual-face packages, then electrodes can be formed on both faces of the package, but the manufacturing process becomes complex and requires high-temperature treatment that is difficult to apply in semiconductor packaging
Solution Approach 1:
The patent divides the electrode formation process into separate stages: inner lead portions are formed on the substrate, then outer lead portions are added later through wire bonding or other connection methods. This segmentation eliminates the need for complex through-hole formation and insulation processes, allowing dual-face electrodes to be created through simpler, sequential steps that are compatible with standard semiconductor packaging processes.
2Adaptability or versatility
If through holes are formed in semiconductor substrate for dual-face packaging, then external connections can be established on both faces, but the high-temperature treatment required makes the process difficult to apply
Solution Approach 1:
The patent extracts the high-temperature through-hole formation process from the electrode creation process. Instead of forming through holes in the substrate, the invention uses pre-formed inner lead portions that can be connected to outer lead portions through low-temperature methods such as wire bonding, thereby achieving dual-face external connections without subjecting the semiconductor substrate to high-temperature treatment.
3Adaptability or versatility
If conventional dual-face package technology is used, then electrodes are available on both faces, but the through-silicon via structure requires complex insulation methods that increase manufacturing difficulty
Solution Approach 1:
The patent performs preliminary action by pre-forming the inner lead portions on the substrate before the packaging process. These inner lead portions are prepared in advance with appropriate insulation and positioning, so that when outer lead portions are added later through wire bonding or other methods, the insulation requirements are already satisfied, greatly simplifying the overall manufacturing process.
Data Source
AI summary
A dual-face package has an LSI chip sealed with a mold resin, and electrodes for external connections on both of the front face and the back face. The LSI chip is bonded onto the die pad of a leadframe whose outer lead portions are exposed as back-face electrodes at least the back face. The LSI chip and a plurality of inner lead portions of the leadframe are connected by wiring. At least some of the plurality of inner lead portions have front-face electrodes integrally formed by working a portion of the leadframe. Head faces of the front-face electrodes, or bump electrodes connected to the respective head faces of the front-face electrodes serve as electrodes for external connections to another substrate, element, or the like.