Leadless Glass Package With Capacitive Die Isolation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional isolation methods for semiconductor circuits face limitations such as bulkiness, limited bandwidth, susceptibility to environmental factors, and reliability issues in leadless packages, particularly due to constraints on insulation distance and the need for specialized coatings to protect against environmental factors.
Innovation Solution
A leadless package design utilizing a glass substrate with integrated capacitive isolation between semiconductor dies, achieved through a galvanic coupling via a bottom electrically conductive plate and top plates, eliminating the need for external components and specialized coatings, and ensuring robust isolation and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional isolation components (optocouplers, capacitors, transformers) are used, then isolation between voltage levels is achieved, but the device becomes bulky and has limited bandwidth
Solution Approach 1:
The patent merges the isolation function with the semiconductor die structure itself by integrating capacitive isolation layers directly into the leadless package. This eliminates the need for separate external isolation components while achieving the required galvanic isolation between different voltage levels, thereby reducing device size while maintaining isolation performance.
Solution Approach 2:
The patent introduces an intermediary capacitive isolation structure composed of metal layers and insulating materials that enables voltage level isolation within the semiconductor package. This intermediary structure provides galvanic isolation without requiring external components, resolving the contradiction between compact size and effective isolation.
2Volume of moving object
If integrated isolators are used within semiconductor components, then device size is reduced, but insulation distance is limited leading to ESD risks
Solution Approach 1:
The patent employs composite material structures combining multiple metal layers with insulating materials (such as glass substrates and dielectric layers) to create an integrated isolation system. This composite approach enables adequate insulation distance and ESD protection within the compact leadless package by leveraging the complementary properties of different materials.
Solution Approach 2:
The patent utilizes the vertical dimension within the semiconductor package by stacking multiple metal and insulating layers to achieve sufficient insulation distance. This multi-layer vertical structure provides the necessary creepage and clearance distances for ESD protection while maintaining a compact overall device footprint.
3Area of stationary object
If leadless package configuration is used, then footprint is reduced and thermal management is improved, but manufacturing complexity increases due to lead frame split
Solution Approach 1:
The patent extracts and eliminates the lead frame component from the package structure, transitioning to a leadless configuration where electrical connections are made through direct bonding or wire bonds to pads on the package substrate. This removal of the lead frame simplifies the manufacturing process by eliminating the complex lead frame splitting and forming operations while achieving reduced footprint.
4Area of stationary object
If leadless package with exposed pad is used, then footprint is reduced, but specialized coatings are needed for environmental protection
Solution Approach 1:
The patent designs the package substrate and sealing structures to serve multiple functions: providing electrical connections, environmental protection, and mechanical support. The glass or ceramic substrate acts as both the mounting platform and the protective barrier, eliminating the need for separate specialized coatings while maintaining the leadless compact configuration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The glass substrate provides enhanced insulation, shielding from electromagnetic interference, simplifies manufacturing, and improves reliability and longevity of semiconductor devices by eliminating the need for additional coatings and external components.
Implementation Method 1
a glass substrate; first and second electrically conductive interconnect route layers provided on a top side of said glass substrate, wherein the first and second electrically conductive interconnect route layers are isolated from each other
Implementation Method 2
a bottom electrically conductive plate provided in or at said top side of said glass substrate, wherein said bottom electrically conductive plate is oriented such that a capacitive coupling is provided between: said first electrically conductive plate and said bottom electrically conductive plate, and said second electrically conductive plate and said bottom electrically conductive plate
Implementation Method 3
The glass substrate provides enhanced insulation, shielding from electromagnetic interference
Data Source
AI summary
A leadless package, including a glass substrate, first and second electrically conductive interconnect route layers provided on a top side of the glass substrate, the first and second electrically conductive interconnect route layers are isolated from each other, first and second electrically conductive top plates provided on the top side of the glass substrate, a first semiconductor die having at least two terminals, a first of the two terminals is connected to the first electrically conductive interconnect route layer and a second of the at least two terminals is connected to the first electrically conductive top plate and a second semiconductor die having at least two terminals, and a first of the two terminals is connected to the second electrically conductive interconnect route layer and a second of the at least two terminals is connected to the second electrically conductive top plate.