Leadless Semiconductor Package Metal Side Pads

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Solution Overview

Problem

Leadless packaged semiconductor devices are difficult to inspect for solder joint defects due to hidden Input/Output terminals, and existing solutions like Automatic X-Ray Inspection are expensive, while conventional methods like Automated Optical Inspection are limited in their ability to inspect solder joints effectively.

Innovation Solution

The solution involves forming metal side pads on the semiconductor device by electroplating terminals after exposing them through parallel cuts in the lead frame structure, and then filling grooves with an insulating material to ensure electrical isolation and facilitate the formation of metal side pads on multiple terminals, allowing for effective Automated Optical Inspection.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If metal side pads are formed by electroplating terminals after first singulation cuts, then inspection capability is improved, but middle I/O terminals become electrically isolated and cannot be plated

Engineering Contradiction:
Improvesolder joint inspection capabilityVSAvoidelectrical continuity for electroplating
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

The patent applies preliminary action by performing electroplating of metal side pads on all I/O terminals (including middle terminals) BEFORE making the second series of parallel singulation cuts. This sequence ensures that middle terminals remain electrically connected to the lead frame during plating, allowing complete coverage. After plating, the singulation cuts electrically isolate the terminals for inspection purposes while the metal side pads remain intact and functional.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent segments the manufacturing process into distinct sequential stages: (1) first singulation cuts to expose terminals, (2) electroplating of all terminals including middle ones, (3) second singulation cuts to electrically isolate terminals. This segmentation allows the process to achieve both electrical continuity during plating and electrical isolation for inspection, resolving the contradiction between these two requirements.

Inventive Principle:
Principle #1Segmentation

2Productivity

If second series of parallel singulation cuts are made after electroplating, then device singulation is achieved, but metal side pads and I/O terminals become electrically isolated preventing further plating

Engineering Contradiction:
Improvedevice singulation efficiencyVSAvoidelectrical continuity for electroplating
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent performs the electroplating operation as a preliminary action BEFORE executing the second series of parallel singulation cuts. This ensures that all I/O terminals, including middle terminals that will be isolated by the cuts, receive the metal side pad coating while still electrically connected to the lead frame. The subsequent singulation cuts then proceed to electrically isolate the terminals without affecting the already-formed metal side pads.

Inventive Principle:
Principle #10Preliminary action

3Adaptability or versatility

If middle I/O terminals are electrically isolated by lead frame structure, then device functionality is maintained, but metal side pads cannot be formed on these terminals

Engineering Contradiction:
Improvedevice functionalityVSAvoidinspection capability
Core Design Contradiction:
Adaptability or versatilityVSMeasurement precision

Solution Approach 1:

The patent applies preliminary action by forming metal side pads on middle I/O terminals BEFORE the lead frame structure electrically isolates them through the second singulation cuts. This sequence allows middle terminals to be plated while maintaining electrical continuity, then subsequently isolated for device functionality. The result is that middle terminals have both the inspection capability provided by metal side pads and the electrical isolation required for proper device operation.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent adds a temporal dimension to the process sequence, changing when the electrical isolation occurs relative to when electroplating occurs. By performing plating in the temporal dimension before isolation, the patent enables middle terminals to receive metal side pads while maintaining continuity during plating, then achieves isolation for functionality afterward. This temporal reordering resolves the contradiction between needing continuity for plating and isolation for functionality.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method enables the inspection of solder joints using Automated Optical Inspection systems, improves mechanical stability, and allows for the formation of metal side pads on four or more terminals, enhancing the inspection and reliability of leadless packaged semiconductor devices.

Implementation Method 1

The process of forming a such leadless device involves dividing a two-dimensional array of encapsulated integrated circuits into individual semiconductor device packages using a series of parallel row cuts and parallel column cuts. The first series of parallel singulation cuts extend fully through the lead frame and encapsulation layer defining rows of the array. In such a process the I/O terminals will be exposed and since the I/O terminals are mutually electrically connected the exposed I/O terminals may be electroplated to form the metal side pads.

Methodology Applied
Scientific EffectElectroplating: Electroplating

Data Source

PatentUS11631634B2Leadless semiconductor package and method of manufacture
Publication Date: 2023.04.18 NEXPERIA BV
  • US11631634B2 patent drawing
  • US11631634B2 patent drawing
  • US11631634B2 patent drawing

AI summary

This disclosure relates to a leadless packaged semiconductor device including a top and a bottom opposing major surfaces and sidewalls extending between the top and bottom surfaces, the leadless packaged semiconductor device further includes a lead frame structure including an array of two or more lead frame sub-structures each having a semiconductor die arranged thereon, and terminals and a track extended across the bottom surface of the semiconductor device. The track provides a region for interconnecting the semiconductor die and terminals, and the track is filled by an insulating material to isolate the lead frame sub-structures.