Leakage Current Detection Circuit for 3D Memory Plane Integrity

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Solution Overview

Problem

In non-volatile semiconductor memory devices, leakage current between a block select line and a shared conductive region can lead to electrical shorts, causing plane-level failures that result in data loss and operational failures, as charges become trapped in the dielectric material over time, affecting the memory array's control and data integrity.

Innovation Solution

A leakage current detection circuit is implemented to identify and measure the current between the block select line and the conductive region, allowing for early detection and prevention of electrical shorts by moving data out of the affected plane before a failure occurs, thereby preventing data loss.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multi-plane parallel operation is implemented to improve memory performance, then productivity increases, but the risk of leakage current causing plane-level failures increases

Engineering Contradiction:
Improvememory operation parallelismVSAvoidplane operational integrity
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent implements preliminary detection of leakage current between block select lines and shared conductive regions before the leakage causes plane-level failures. The detection circuit monitors current levels and generates warnings or errors when threshold values are exceeded, allowing proactive data relocation from affected planes before operational failures occur.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If block select lines extend over multiple blocks to enable parallel operations, then productivity improves, but leakage current between the select line and shared conductive region increases

Engineering Contradiction:
Improveparallel block access capabilityVSAvoidleakage current
Core Design Contradiction:
ProductivityVSObject-generated harmful factors

Solution Approach 1:

The patent implements a feedback mechanism where detection circuits continuously monitor leakage current levels between block select lines and shared conductive regions. When the monitored current exceeds predetermined threshold values, the system generates warnings or errors that trigger data relocation operations, creating a closed-loop control system that prevents plane-level failures.

Inventive Principle:
Principle #23Feedback

3Productivity

If data is stored in planes with extended block select lines for efficient access, then productivity improves, but data loss risk increases due to potential electrical shorts

Engineering Contradiction:
Improvedata access efficiencyVSAvoiddata loss from plane failure
Core Design Contradiction:
ProductivityVSLoss of information

Solution Approach 1:

The patent performs preliminary detection and monitoring of leakage current conditions before they escalate to plane-level failures that would cause data loss. By detecting current levels exceeding threshold values and generating warnings in advance, the system enables proactive data relocation from at-risk planes, preventing information loss while maintaining efficient data storage in multi-plane structures.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20180061505A1Leakage Current Detection In 3D Memory
Publication Date: 2018.03.01 SANDISK TECHNOLOGIES LLC
  • US20180061505A1 patent drawing
  • US20180061505A1 patent drawing
  • US20180061505A1 patent drawing

AI summary

Technology is described herein for detecting a leakage current between a block select line and a conductive region that exists in multiple blocks of memory cells in a plane. The conductive region may be shared by at least one memory cell in multiple blocks. One example of the conductive region is a common source line that includes one or more local source lines and one or more global source lines. If the leakage current were to become high enough, the electrical short between the conductive region and the block select line could cause a plane level failure. If the leakage current is less than an amount that would cause a plane failure, but that indicates that the non-volatile memory device is susceptible to a plane failure, data may be moved out of the plane before the plane failure occurs. Thus, data loss may be prevented.