LED Array PCB Layout With Shared Routing to Cut Via Holes
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Solution Overview
Problem
The high defect rate and increased production cost of LED display screens due to the need for numerous holes and additional layers in PCB boards, which complicates the manufacturing process and increases material costs.
Innovation Solution
An LED arrangement structure where LEDs are arranged in a specific array on a PCB board with common-electrode terminals connected to scanning lines in one layer and non-common-electrode terminals connected to data lines in another layer, reducing the number of via holes and eliminating the need for additional board width or layers, thereby lowering production costs and improving yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If numerous via holes are used to connect LED terminals to data lines and scanning lines, then electrical connectivity is improved, but the defect rate of PCB board increases and production cost increases
Solution Approach 1:
The patent merges the connection paths of multiple LED terminals by routing them through shared via holes. Specifically, multiple data lines or scanning lines are connected to multiple LED terminals through common via holes, reducing the total number of via holes required while maintaining proper electrical connectivity across the LED array.
Solution Approach 2:
The via holes are designed to serve multiple functions simultaneously. A single via hole connects not only one LED terminal to its corresponding data or scanning line but also serves as a shared connection point for multiple adjacent LED terminals, making the via hole a multi-functional connection element that reduces overall complexity.
2Reliability
If the width or number of layers of PCB board is increased to accommodate more via holes and routing, then connectivity is improved, but material cost increases greatly
Solution Approach 1:
The patent utilizes the vertical dimension of the PCB board by implementing multi-layer routing architecture. Data lines and scanning lines are arranged on different layers, with via holes providing vertical inter-layer connections. This three-dimensional routing approach allows efficient connectivity without increasing the horizontal board area, thereby avoiding additional material costs.
Solution Approach 2:
The routing structure employs a nested arrangement where via holes are strategically positioned to serve multiple routing layers simultaneously. The via hole network is nested within the multi-layer PCB structure, with each via hole potentially connecting multiple layers, thus maximizing the use of existing board material without requiring additional board width or layers.
3Ease of manufacture
If the number of via holes is reduced to lower production cost, then material cost decreases, but the complexity of routing and connection increases
Solution Approach 1:
The LED array is segmented into groups where each group shares common connection via holes. By dividing the LED matrix into logical segments and providing shared via hole connections for each segment, the routing complexity is managed systematically rather than requiring individual unique paths for every LED terminal, thus reducing overall complexity while maintaining connectivity.
4Reliability
If via holes are increased to ensure proper connection of all LED terminals, then connection reliability is improved, but the yield of PCB board decreases
Solution Approach 1:
Multiple LED terminal connections are merged into shared via holes, ensuring that each via hole provides reliable electrical connection for multiple terminals simultaneously. This merging approach maintains connection reliability while reducing the total via hole count, thereby improving PCB board yield without sacrificing connection quality.
Data Source
AI summary
An LED arrangement structure is provided with a plurality of LEDs arranged in an array in the first direction and the second direction to form a plurality of LED rows and a plurality of LED columns, each of the LED rows includes a plurality of LED groups, and each of the LED groups includes two adjacent LEDs. Two non-common-electrode terminals in each of LED groups in at least one of the LED rows are connected to each other on a surface layer of the PCB board.